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| STM8L101xx 8-bit ultralow power microcontroller with up to 8 Kbytes Flash, multifunction timers, comparators, USART, SPI, I2C Preliminary data Features Main microcontroller features - Supply voltage range 1.65 V to 3.6 V - Low power consumption (Halt: 0.3 A, Active-halt: 0.8 A, Dynamic Run: 150 A/MHz) - STM8 Core with up to 16 CISC MIPS throughput - Temp. range: -40 to 85 C and 125 C Memories - Up to 8 Kbytes of Flash program including up to 2 Kbytes of data EEPROM - Error correction code (ECC) - Flexible write and read protection modes - In-application and in-circuit programming - Data EEPROM capability - 1.5 Kbytes of static RAM Clock management - Internal 16 MHz RC with fast wakeup time (typ. 4 s) - Internal low consumption 38 kHz RC driving both the IWDG and the AWU Reset and supply management - Ultralow power, ultrasafe power-on-reset /power down reset - Three low power modes: Wait, Active-halt, Halt Interrupt management - Nested interrupt controller with software priority control - Up to 29 external interrupt sources I/Os - Up to 30 I/Os, all mappable on external interrupt vectors - I/Os with prog. input pull-ups, high sink/source capability and one LED driver infrared output WFQFPN32 LQFP32 WFQFPN28 UFQFPN20 TSSOP20 Peripherals - Two 16-bit general purpose timers (TIM2 and TIM3) with up and down counter and 2 channels (used as IC, OC, PWM) - One 8-bit timer (TIM4) with 7-bit prescaler - Infrared remote control (IR) - Independent watchdog - Auto-wakeup unit - Beeper timer with 1, 2 or 4 kHz frequencies - SPI synchronous serial interface - Fast I2C Multimaster/slave 400 kHz - USART with fractional baud rate generator - 2 comparators with 4 inputs each Development support - Hardware single wire interface module (SWIM) for fast on-chip programming and non intrusive debugging - In-circuit emulation (ICE) 96-bit unique ID Device summary Part number STM8L101F2, STM8L101F3, STM8L101G2, STM8L101G3 STM8L101K3 Table 1. Reference STM8L101xx September 2009 Doc ID 15275 Rev 7 1/77 www.st.com 1 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. Contents STM8L101xx Contents 1 2 3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Product overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 Central processing unit STM8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Single wire data interface (SWIM) and debug module . . . . . . . . . . . . . . . 10 Interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Voltage regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Clock control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Independent watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Auto-wakeup counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 General purpose and basic timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Infrared (IR) interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 IC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4 5 6 7 8 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Memory and register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Interrupt vector mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Unique ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2/77 Doc ID 15275 Rev 7 STM8L101xx Contents 9 Electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 9.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 9.1.1 9.1.2 9.1.3 9.1.4 9.1.5 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 9.2 9.3 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 9.3.1 9.3.2 9.3.3 9.3.4 9.3.5 9.3.6 9.3.7 9.3.8 9.3.9 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Power-up / power-down operating conditions . . . . . . . . . . . . . . . . . . . . 41 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 9.4 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 10 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 10.1 10.2 ECOPACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 11 12 Device ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 STM8 development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 12.1 12.2 Emulation and in-circuit debugging tools . . . . . . . . . . . . . . . . . . . . . . . . . 72 Software tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 12.2.1 12.2.2 STM8 toolset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 C and assembly toolchains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 12.3 Programming tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 13 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Doc ID 15275 Rev 7 3/77 List of tables STM8L101xx List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Device features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Legend/abbreviation for table 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 STM8L101xx pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Flash and RAM boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 I/O Port hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 General hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 CPU/SWIM/debug module/interrupt controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Unique ID registers (96 bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Total current consumption in Run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Total current consumption in Wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Total current consumption and timing in Halt and Active-halt mode at VDD = 1.65 V to 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 HSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Flash program memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Output driving current (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Output driving current (true open drain ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Output driving current (PA0 with high sink LED driver capability). . . . . . . . . . . . . . . . . . . . 52 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 I2C characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 EMS data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 EMI data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 WFQFPN32 - 32-lead very very thin fine pitch quad flat no-lead package (5 x 5), package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 LQFP32- 32-pin low profile quad flat package (7x7), package mechanical data . . . . . . . . 67 WFQFPN28 - 28-lead very very thin fine pitch quad flat no-lead package (4 x 4), package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 UFQFPN20 3 x 3 mm 0.6 mm mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 20-lead thin shrink small package, mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 4/77 Doc ID 15275 Rev 7 STM8L101xx List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. STM8L101 device block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Standard 20-pin UFQFPN package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 20-pin UFQFPN package pinout for STM8L101F3U6ATR and STM8L101F2U6ATR part numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 20-pin TSSOP package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Standard 28-pin WFQFPN package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 28-pin WFQFPN package pinout for STM8L101G3U6ATR and STM8L101G2U6ATR part numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 32-pin package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 IDD(RUN) vs. VDD@ fCPU = 2 MHz @4 temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 IDD(RUN) vs. VDD@ fCPU = 16 MHz @4 temperatures. . . . . . . . . . . . . . . . . . . . . . . . . . 41 IDD(WAIT) vs. VDD@ fCPU = 2 MHz @4 temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 IDD(WAIT) vs. VDD@ fCPU = 16 MHz @4 temperatures . . . . . . . . . . . . . . . . . . . . . . . . . 42 Typ. IDD(Halt) vs. VDD @ fCPU = 2 MHz and 16 MHz @4 temperatures. . . . . . . . . . . . . 43 Typical HSI frequency vs VDD @ 4 temperatures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Typical HSI accuracy at VDD = 3 V vs temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Typical HSI accuracy at VDD = 1.65 V to 3.6 V vs temperature. . . . . . . . . . . . . . . . . . . . . 46 Typical LSI RC frequency vs. VDD @ 4 temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Typical VIL and VIH vs VDD (standard I/Os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Typical VIL and VIH vs VDD (true open drain I/Os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Typical pull-up resistance RPU vs VDD @ 4 temperatures with VIN=VSS . . . . . . . . . . . . . 50 Typical pull-up current Ipu vs VDD @ 4 temperatures with VIN=VSS . . . . . . . . . . . . . . . . . 51 Typ. VOL @ VDD = 3.0 V (standard ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Typ. VOL @ VDD = 1.8 V (standard ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Typ. VOL @ VDD = 3.0 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Typ. VOL @ VDD = 1.8 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Typ. VDD - VOH @ VDD = 3.0 V (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Typ. VDD - VOH @ VDD = 1.8 V (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Typical NRST pull-up resistance RPU vs VDD @ 4 temperatures . . . . . . . . . . . . . . . . . . . . 54 Typical NRST pull-up current Ipu vs VDD @ 4 temperatures . . . . . . . . . . . . . . . . . . . . . . . 55 Recommended NRST pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Typical application with I2C bus and timing diagram 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 WFQFPN32 - 32-lead very very thin fine pitch quad flat no-lead package outline (5 x 5) . 65 WFQFPN32 recommended footprint(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 LQFP32 - 32-pin low profile quad flat package outline (7 x 7) . . . . . . . . . . . . . . . . . . . . . . 67 LQFP32 recommended footprint(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 WFQFPN28 - 28-lead very very thin fine pitch quad flat no-lead package outline (4 x 4) . 68 WFQFPN28 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 UFQFPN20 3 x 3 mm 0.6 mm package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 UFQFPN20 recommended footprint (1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Doc ID 15275 Rev 7 5/77 List of figures Figure 45. Figure 46. Figure 47. STM8L101xx TSSOP20 - 20-lead thin shrink small package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 TSSOP20 recommended footprint (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 STM8L101xx ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 6/77 Doc ID 15275 Rev 7 STM8L101xx Introduction 1 Introduction This datasheet provides the STM8L101xx pinout, ordering information, mechanical and electrical device characteristics. For complete information on the STM8L101xx microcontroller memory, registers and peripherals, please refer to the STM8L reference manual. 2 Description The STM8L101xx devices are members of the STM8L low power 8-bit family. All devices of the SM8L product line provide the following benefits: Reduced system cost - - - Up to 8 Kbytes of embedded Flash program memory including up to 2 Kbytes of data EEPROM High system integration level with internal clock oscillators and watchdogs. Smaller battery and cheaper power supplies. Up to 16 MIPS at 16 MHz CPU clock frequency less than 150 A/MH, 0.8 A in Active-halt mode, and 0.3 A in Halt mode Clock gated system and optimized power management Application scalability across a common family product architecture with compatible pinout, memory map and modular peripherals. Full documentation and a wide choice of development tools Advanced core and peripherals made in a state-of-the art technology Product family operating from 1.65 V to 3.6 V supply Low power consumption and advanced features - - - Short development cycles - - Product longevity - - The STM8L101xx low power family features the enhanced STM8 CPU core providing increased processing power (up to 16 MIPS at 16 MHz) while maintaining the advantages of a CISC architecture with improved code density, a 24-bit linear addressing space and an optimized architecture for low power operations. The family includes an integrated debug module with a hardware interface (SWIM) which allows non-intrusive In-Application debugging and ultrafast Flash programming. All STM8L101xx microcontrollers feature low power low-voltage single-supply program Flash memory. The 8-Kbyte devices embed data EEPROM. The STM8L101xx low power family is based on a generic set of state-of-the-art peripherals. The modular design of the peripheral set allows the same peripherals to be found in different ST microcontroller families including 32-bit families. This makes any transition to a different family very easy, and simplified even more by the use of a common set of development tools. Doc ID 15275 Rev 7 7/77 Description STM8L101xx All STM8L low power products are based on the same architecture with the same memory mapping and a coherent pinout. Table 2. Device features Features Flash RAM STM8L101xx 4 Kbytes of Flash program memory 8 Kbytes of Flash program memory including up to 2 Kbytes of Data EEPROM 1.5 Kbytes Independent watchdog (IWDG), Auto-wakeup unit (AWU), Beep, Serial peripheral interface (SPI), Inter-integrated circuit (IC), Universal synchronous / asynchronous receiver / transmitter (USART), 2 comparators, Infrared (IR) interface Two 16-bit timers, one 8-bit timer 1.65 to 3.6 V -40 to +85 C WFQFPN28 4x 4 UFQFPN20 3x3 TSSOP20 4.4 x 6.4 -40 to +85 C or -40 to +125 C WFQFPN28 4x4 UFQFPN20 3x3 WFQFPN32 LQFP32 Peripheral functions Timers Operating voltage Operating temperature Packages 8/77 Doc ID 15275 Rev 7 STM8L101xx Product overview 3 Product overview Figure 1. STM8L101 device block diagram @VDD VDD18 Power Volt. reg. 16 MHz int RC 38 kHz int RC Clock controller Clocks to core and peripherals VDD =1.65 V to 3.6 V VSS Reset POR/PDR NRST STM8 Core up to 16 MHz Nested interrupt controller up to 29 external interrupts Debug module (SWIM) Address and data bus Up to 8 Kbytes Flash memory (including up to 2 Kbytes data EEPROM) 1.5 Kbytes SRAM SWIM USART IC1 multimaster SPI 16-bit Timer 2 16-bit Timer 3 8-bit Timer 4 IWDG AWU RX, TX, CK SDA, SCL IR_TIM Infrared interface MOSI, MISO, SCK, NSS TIM2_CH[2:1] TIM2_TRIG TIM3_CH[2:1] TIM3_TRIG PA[6:0] PB[7:0] PC[6:0] PD[7:0] Port A Port B Port C Port D COMP1_CH[4:1] COMP1 COMP_REF COMP2_CH[4:1] COMP2 Beeper BEEP Legend: AWU: Auto-wakeup unit Int. RC: internal RC oscillator IC: Inter-integrated circuit multimaster interface POR/PDR: Power on reset / power down reset SPI: Serial peripheral interface SWIM: Single wire interface module USART: Universal synchronous / asynchronous receiver / transmitter IWDG: Independent watchdog Doc ID 15275 Rev 7 9/77 Product overview STM8L101xx 3.1 Central processing unit STM8 The 8-bit STM8 core is designed for code efficiency and performance. It features 21 internal registers, 20 addressing modes including indexed, indirect and relative addressing, and 80 instructions. 3.2 Development tools Development tools for the STM8 microcontrollers include: The STice emulation system offering tracing and code profiling The STVD high-level language debugger including C compiler, assembler and integrated development environment The STVP Flash programming software The STM8 also comes with starter kits, evaluation boards and low-cost in-circuit debugging/programming tools. 3.3 Single wire data interface (SWIM) and debug module The debug module with its single wire data interface (SWIM) permits non-intrusive real-time in-circuit debugging and fast memory programming. The Single wire interface is used for direct access to the debugging module and memory programming. The interface can be activated in all device operation modes. The non-intrusive debugging module features a performance close to a full-featured emulator. Beside memory and peripherals, also CPU operation can be monitored in realtime by means of shadow registers. 3.4 Interrupt controller The STM8L101xx features a nested vectored interrupt controller: Nested interrupts with 3 software priority levels 26 interrupt vectors with hardware priority Up to 29 external interrupt sources on 10 vectors Trap and reset interrupts 10/77 Doc ID 15275 Rev 7 STM8L101xx Product overview 3.5 Memory The STM8L101xx devices have the following main features: 1.5 Kbytes of RAM The EEPROM is divided into two memory arrays (see the STM8L reference manual for details on the memory mapping): - Up to 8 Kbytes of embedded Flash program including up to 2 Kbytes of data EEPROM. Data EEPROM and Flash program areas can be write protected independently by using the memory access security mechanism (MASS). 64 option bytes (one block) of which 5 bytes are already used for the device. - Error correction code is implemented on the EEPROM. 3.6 Low power modes To minimize power consumption, the product features three low power modes: Wait mode: CPU clock stopped, selected peripherals at full clock speed. Active-halt mode: CPU and peripheral clocks are stopped. The programmable wakeup time is controlled by the AWU unit. Halt mode: CPU and peripheral clocks are stopped, the device remains powered on. Wakeup is triggered by an external interrupt. 3.7 Voltage regulators The STM8L101xx embeds an internal voltage regulator for generating the 1.8 V power supply for the core and peripherals. This regulator has two different modes: main voltage regulator mode (MVR) and low power voltage regulator mode (LPVR). When entering Halt or Active-halt modes, the system automatically switches from the MVR to the LPVR in order to reduce current consumption. 3.8 Clock control The STM8L101xx embeds a robust clock controller. It is used to distribute the system clock to the core and the peripherals and to manage clock gating for low power modes. This system clock is a 16-MHz High Speed Internal RC oscillator (HSI RC), followed by a programmable prescaler. In addition, a 38 kHz low speed internal RC oscillator is used by the independent watchdog (IWDG) and Auto-wakeup unit (AWU). 3.9 Independent watchdog The independent watchdog (IWDG) peripheral can be used to resolve processor malfunctions due to hardware or software failures. It is clocked by the 38 kHZ LSI internal RC clock source, and thus stays active even in case of a CPU clock failure. Doc ID 15275 Rev 7 11/77 Product overview STM8L101xx 3.10 Auto-wakeup counter The auto-wakeup (AWU) counter is used to wakeup the device from Active-halt mode. 3.11 General purpose and basic timers STM8L101xx devices contain two 16-bit general purpose timers (TIM2 and TIM3) and one 8-bit basic timer (TIM4). 16-bit general purpose timers The 16-bit timers consist of 16-bit up/down auto-reload counters driven by a programmable prescaler. They perform a wide range of functions, including: Time base generation Measuring the pulse lengths of input signals (input capture) Generating output waveforms (output compare, PWM and one pulse Mode) Interrupt capability on various events (capture, compare, overflow, break, trigger) Synchronization with other timers or external signals (external clock, reset, trigger and enable) 8-bit basic timer The 8-bit timer consists of an 8-bit up auto-reload counter driven by a programmable prescaler. It can be used for timebase generation with interrupt generation on timer overflow. 3.12 Beeper The STM8L101xx devices include a beeper function used to generate a beep signal in the range of 1, 2 or 4 kHz when the LSI clock is operating at a frequency of 38 kHz. 3.13 Infrared (IR) interface The STM8L101xx devices contain an infrared interface which can be used with an IR LED for remote control functions. Two timer output compare channels are used to generate the infrared remote control signals. 3.14 Comparators The STM8L101xx features two zero-crossing comparators (COMP1 and COMP2) sharing the same current bias and voltage reference. The voltage reference can be internal (comparison with ground) or external (comparison to a reference pin voltage). Each comparator is connected to 4 channels, which can be used to generate interrupt, timer input capture or timer break. Their polarity can be inverted. 12/77 Doc ID 15275 Rev 7 STM8L101xx Product overview 3.15 USART The USART interface (USART) allows full duplex, asynchronous communications with external devices requiring an industry standard NRZ asynchronous serial data format. It offers a very wide range of baud rates. 3.16 SPI The serial peripheral interface (SPI) provides half/ full duplex synchronous serial communication with external devices. It can be configured as the master and in this case it provides the communication clock (SCK) to the external slave device. The interface can also operate in multi-master configuration. 3.17 IC The inter-integrated circuit (I2C) Bus Interface is designed to serve as an interface between the microcontroller and the serial I2C bus. It provides multi-master capability, and controls all IC bus-specific sequencing, protocol, arbitration and timing. It manages standard and fast speed modes. Doc ID 15275 Rev 7 13/77 Pin description STM8L101xx 4 Pin description Figure 2. Standard 20-pin UFQFPN package pinout PA0 (HS) / SWIM / BEEP / IR_TIM PC4 (HS) / USART_CK / CCO PC2 (HS) / USART_RX PC3 (HS) / USART_TX 20 19 18 17 16 15 14 13 12 11 NRST / PA1 (HS) PA2 (HS) PA3 (HS) VSS VDD 1 2 3 4 5 6 7 8 9 10 PC1 / IC_SCL PC0 / IC_SDA PB7 (HS) / SPI_MISO PB6 (HS) / SPI_MOSI PB5 (HS) / SPI_SCK PB4 (HS) / SPI_NSS 1. HS corresponds to 20 mA high sink/source capability. 2. High sink LED driver capability available on PA0. Refer to the description of the IR_CR register in the STM8L reference manual (RM0013). Note: The COMP_REF pin is not available in this standard 20-pin UFQFPN package. It is available on Port A6 in the 20-pin UFQFPN package pinout for STM8L101F3U6ATR and STM8L101F2U6ATR part numbers (Figure 3 on page 15). 14/77 Doc ID 15275 Rev 7 PB3 (HS) / TIM2_TRIG / COMP2_CH2 PB0 (HS) / TIM2_CH1 / COMP1_CH1 PB1 (HS) / TIM3_CH1 /COMP1_CH2 PD0 (HS) / TIM3_CH2 / COMP1_CH3 PB2 (HS) / TIM2_CH2 / COMP2_CH1 STM8L101xx Figure 3. Pin description 20-pin UFQFPN package pinout for STM8L101F3U6ATR and STM8L101F2U6ATR part numbers PA0 (HS) / SWIM / BEEP / IR_TIM PC4 (HS) / USART_CK / CCO PC2 (HS) / USART_RX PC3 (HS) / USART_TX 20 19 18 17 16 15 14 13 12 11 NRST / PA1 (HS) PA2 (HS) PA6 (HS) / COMP_REF VSS VDD 1 2 3 4 5 6 7 8 9 10 PC1 / IC_SCL PC0 / IC_SDA PB7 (HS) / SPI_MISO PB6 (HS) / SPI_MOSI PB5 (HS) / SPI_SCK PB4 (HS) / SPI_NSS 1. Please refer to the warning below. 2. HS corresponds to 20 mA high sink/source capability. 3. High sink LED driver capability available on PA0. Refer to the description of the IR_CR register in the STM8L reference manual (RM0013). Warning: For the STM8L101F3U6ATR and STM8L101F2U6ATR part numbers (devices with COMP_REF pin), all ports available on 32-pin packages must be considered as active ports. To avoid spurious effects, you have to configure them as input pull-up. A small increase in consumption (typ. < 300 A) may occur during the power up and reset phase until these ports are properly configured . Doc ID 15275 Rev 7 PB3 (HS) / TIM2_TRIG / COMP2_CH2 PD0 (HS) / TIM3_CH2 / COMP1_CH3 PB0 (HS) / TIM2_CH1 / COMP1_CH1 PB2 (HS) / TIM2_CH2 / COMP2_CH1 PB1 (HS) / TIM3_CH1 /COMP1_CH2 15/77 Pin description Figure 4. 20-pin TSSOP package pinout STM8L101xx PC3 (HS) / USART_TX PC4 (HS) / USART_CK/ CCO PA0 (HS) / SWIM / BEEP / IR_TIM NRST / PA1 (HS) PA2 (HS) PA3 (HS) VSS VDD PD0 (HS) / TIM3_CH2 / COMP1_CH3 PB0 (HS) / TIM2_CH1 / COMP1_CH1 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 PC2 (HS) / USART_RX PC1 / IC_SCL PC0 / IC_SDA PB7 (HS) / SPI_MISO PB6 (HS) / SPI_MOSI PB5 (HS) / SPI_SCK PB4 (HS) / SPI_NSS PB3 (HS) /TIM2_TRIG /COMP2_CH2 PB2 (HS) / TIM2_CH2 / COMP2_CH1 PB1 (HS) / TIM3_CH1 / COMP1_CH2 1. HS corresponds to 20 mA high sink/source capability. 2. High sink LED driver capability available on PA0. Refer to the description of the IR_CR register in the STM8L reference manual (RM0013). 16/77 Doc ID 15275 Rev 7 STM8L101xx Figure 5. Standard 28-pin WFQFPN package pinout PA0 (HS) / SWIM / BEEP / IR_TIM PC4 (HS) / USART_CK / CCO Pin description PC2 (HS) / USART_RX 23 PC3 (HS) / USART_TX 28 27 26 25 24 PC1 / IC_SCL 22 21 20 19 18 17 16 15 PC6 (HS) PC5 (HS) NRST / PA1 (HS) PA2 (HS) PA3 (HS) PA4 (HS) / TIM2_BKIN PA5 (HS) / TIM3_BKIN VSS VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PC0 / IC_SDA PD4 (HS) PB7 (HS) / SPI_MISO PB6 (HS) / SPI_MOSI PB5 (HS) / SPI_SCK PB4 (HS) / SPI_NSS PB3 (HS) / TIM2_TRIG / COMP2_CH2 PD1 (HS) / TIM3_TRIG / COMP1_CH4 PD2(HS) / COMP2_CH3 PD0 (HS) / TIM3_CH2 / COMP1_CH3 / COMP2_CH4 PB0 (HS) / TIM2_CH1 / COMP1_CH1 PB1 (HS) / TIM3_CH1 / COMP1_CH2 1. HS corresponds to 20 mA high sink/source capability. 2. High sink LED driver capability available on PA0. Refer to the description of the IR_CR register in the STM8L reference manual (RM0013). Note: The COMP_REF pin is not available in this standard 28-pin WFQFPN package. It is available on Port A6 in the 28-pin WFQFPN package pinout for STM8L101G3U6ATR and STM8L101G2U6ATR part numbers (Figure 6 on page 18). Doc ID 15275 Rev 7 PB2 (HS) / TIM2_CH2 / COMP2_CH1 PD3(HS) 17/77 Pin description Figure 6. 28-pin WFQFPN package pinout for STM8L101G3U6ATR and STM8L101G2U6ATR part numbers PA0 (HS) / SWIM / BEEP / IR_TIM PC4 (HS) / USART_CK / CCO STM8L101xx PC2 (HS) / USART_RX 23 PC3 (HS) / USART_TX 28 27 26 25 24 PC1 / IC_SCL 22 21 20 19 18 17 16 15 PC6 (HS) PC5 (HS) NRST / PA1 (HS) PA2 (HS) PA3 (HS) PA4 (HS) / TIM2_BKIN PA6 (HS) / COMP_REF VSS VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PC0 / IC_SDA PD4 (HS) PB7 (HS) / SPI_MISO PB6 (HS) / SPI_MOSI PB5 (HS) / SPI_SCK PB4 (HS) / SPI_NSS PB3 (HS) / TIM2_TRIG / COMP2_CH2 PD1 (HS) / TIM3_TRIG / COMP1_CH4 PD2(HS) / COMP2_CH3 PD0 (HS) / TIM3_CH2 / COMP1_CH3 PD3(HS) / COMP2_CH4 PB0 (HS) / TIM2_CH1 / COMP1_CH1 PB1 (HS) / TIM3_CH1 / COMP1_CH2 1. HS corresponds to 20 mA high sink/source capability. 2. High sink LED driver capability available on PA0. Refer to the description of the IR_CR register in the STM8L reference manual (RM0013). Warning: For the STM8L101G3U6ATR and STM8L101G2U6ATR part numbers (devices with COMP_REF pin), all ports available on 32-pin packages must be considered as active ports. To avoid spurious effects, you have to configure them as input pull-up. A small increase in consumption (typ. < 300 A) may occur during the power up and reset phase until these ports are properly configured . 18/77 Doc ID 15275 Rev 7 PB2 (HS) / TIM2_CH2 / COMP2_CH1 STM8L101xx Figure 7. 32-pin package pinout PA0 (HS) / SWIM / BEEP / IR_TIM Pin description PC4 (HS) / USART_CK / CCO PC2 (HS) / USART_RX PC3 (HS) / USART_TX 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 PC0 / IC_SDA PC1 / IC_SCL PC6 (HS) PC5 (HS) NRST / PA1 (HS) PA2 (HS) PA3 (HS) PA4 (HS) / TIM2_BKIN PA5 (HS) / TIM3_BKIN PA6 (HS) / COMP_REF VSS VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PD7 (HS) PD6 (HS) PD5 (HS) PD4 (HS) PB7 (HS) / SPI_MISO PB6 (HS) / SPI_MOSI PB5 (HS) / SPI_SCK PB4 (HS) / SPI_NSS PD1 (HS) / TIM3_TRIG / COMP1_CH4 1. Example given for the WFQFPN32 package. The pinout is the same for the LQFP32 package. 2. HS corresponds to 20 mA high sink/source capability. 3. High sink LED driver capability available on PA0. Refer to the description of the IR_CR register in the STM8L reference manual (RM0013). Doc ID 15275 Rev 7 PB3 (HS) / TIM2_TRIG / COMP2_CH2 PB0 (HS) / TIM2_CH1 / COMP1_CH1 PB1 (HS) / TIM3_CH1 / COMP1_CH2 PD0 (HS) / TIM3_CH2 / COMP1_CH3 PB2 (HS) / TIM2_CH2 / COMP2_CH1 PD2 (HS) / / COMP2_CH3 PD3 (HS) / COMP2_CH4 19/77 Pin description Table 3. Type Level Output Port and control Input configuration Output HS = high sink/source (20 mA) float = floating, wpu = weak pull-up T = true open drain, OD = open drain, PP = push pull STM8L101xx Legend/abbreviation for table 4 I= input, O = output, S = power supply Input CM = CMOS Reset state is shown in bold. Table 4. STM8L101xx pin description Input Output Pin number WFQFPN28 with COMP_REF(1) UFQFPN20 with COMP_REF(1) WFQFPN32 or LQFP32 standard WFQFPN28 standard UFQFPN20 wpu OD Pin name High sink/source Ext. interrupt TSSOP20 Main function (after reset) Reset Port A2 Port A3 Port A4 Port A5 Port A6 Ground Port D0 Port D1 Port D2 Port D3 Port B0 Type floating Alternate function 1 2 3 4 5 6 1 2 3 4 5 6 4 5 6 7 8 9 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 9 NRST/PA1(2) PA2 PA3 PA4/TIM2_BKIN PA5/TIM3_BKIN PA6/COMP_REF VSS VDD PD0/TIM3_CH2/ COMP1_CH3 PD1/TIM3_TRIG/ COMP1_CH4 PD2/ COMP2_CH3 PD3/ COMP2_CH4 PB0/TIM2_CH1/ COMP1_CH1 I/O I/O X I/O X I/O X I/O X I/O X S S I/O X X X X X X X X X X X X X HS X HS X HS X HS X HS X HS X X X X X X X PP PA1 Timer 2 - break input Timer 3 - break input Comparator external reference Power supply HS X X Timer 3 - channel 2 / Comparator 1 channel 3 Timer 3 - trigger / Comparator 1 channel 4 Comparator 2 channel 3 Comparator 2 channel 4 Timer 2 - channel 1 / Comparator 1 channel 1 - - - 9 9 10 I/O X X X HS X X - - - 10 10 11 11 11 12 I/O X I/O X X X X X HS X HS X X X 7 7 10 12 12 13 I/O X X X HS X X 20/77 Doc ID 15275 Rev 7 STM8L101xx Table 4. STM8L101xx pin description (continued) Input Output Pin description Pin number WFQFPN28 with COMP_REF(1) UFQFPN20 with COMP_REF(1) WFQFPN32 or LQFP32 standard WFQFPN28 standard UFQFPN20 High sink/source Ext. interrupt TSSOP20 Main function (after reset) Port B1 Port B2 Port B3 Port B4 Port B5 Port B6 Port B7 Port D4 Port D5 Port D6 Port D7 Port C0 Port C1 Port C2 Port C3 Port C4 Port C5 Type floating wpu OD Pin name Alternate function PP 8 8 11 13 13 14 PB1/TIM3_CH1/ COMP1_CH2 PB2/ TIM2_CH2/ COMP2_CH1/ PB3/TIM2_TRIG/ COMP2_CH2 PB4/SPI_NSS PB5/SPI_SCK PB6/SPI_MOSI PB7/SPI_MISO PD4 PD5 PD6 PD7 PC0/I2C_SDA PC1/I2C_SCL PC2/USART_RX PC3/USART_TX I/O X X X HS X X Timer 3 - channel 1 / Comparator 1 channel 2 Timer 2 - channel 2 / Comparator 2 channel 1 Timer 2 - trigger / Comparator 2 channel 2 SPI master/slave select SPI clock SPI master out/ slave in SPI master in/ slave out 9 9 12 14 14 15 I/O X X X HS X X 10 10 13 15 15 16 I/O X X X HS X X 11 12 13 14 15 16 17 18 19 - 11 12 13 14 15 16 17 18 19 - 14 16 16 17 15 17 17 18 16 18 18 19 17 19 19 20 20 20 21 22 23 24 I/O X I/O X I/O X I/O X I/O X I/O X I/O X I/O X I/O X I/O X I/O X I/O X X X X X X X X X X X X X X X X X X X X X X X X X X X X X HS X HS X HS X HS X HS X HS X HS X HS X T T (3) (3) X X X X X X X X 18 21 21 25 19 22 22 26 20 23 23 27 1 2 24 24 28 25 25 29 26 26 30 I2C data I2C clock USART receive USART transmit USART synchronous clock / Configurable clock output HS X HS X HS X HS X X X X X PC4/USART_CK/ I/O X CCO PC5 I/O X Doc ID 15275 Rev 7 21/77 Pin description Table 4. STM8L101xx pin description (continued) Input Output STM8L101xx Pin number WFQFPN28 with COMP_REF(1) UFQFPN20 with COMP_REF(1) WFQFPN32 or LQFP32 standard WFQFPN28 standard UFQFPN20 High sink/source Ext. interrupt TSSOP20 Main function (after reset) Port C6 Port A0 Type floating wpu OD Pin name Alternate function - - - 27 27 31 PC6 I/O X X X HS X HS( 4) X PP 20 20 3 28 28 32 PA0/SWIM/BEEP/ I/O X IR_TIM (4) X X X X SWIM input and output /Beep output/Timer Infrared output 1. Please refer to the warning below. 2. When the PA1/NRST pin is used as general purpose (PA1), it can be configured only as output open-drain or push-pull, not as a general purpose input. Refer to Section 7.1.2: Configuring NRST/PA1 pin as general purpose output. 3. In the open-drain output column, `T' defines a true open-drain I/O (P-buffer and protection diode to VDD are not implemented). 4. High sink LED driver capability available on PA0. Warning: For the STM8L101F2U6ATR, STM8L101F3U6ATR, STM8L101G2U6ATR and STM8L101G3U6ATR part numbers (devices with COMP_REF pin), all ports available on 32-pin packages must be considered as active ports. To avoid spurious effects, you have to configure them as input pull-up. A small increase in consumption (typ. < 300 A) may occur during the power up and reset phase until these ports are properly configured . 22/77 Doc ID 15275 Rev 7 STM8L101xx Memory and register map 5 Memory and register map Figure 8. Memory map 0x00 0000 RAM (1.5 Kbytes) (1) including Stack (up to 513 bytes) (1) Reserved 0x00 47FF 0x00 4800 Option bytes 0x00 48FF 0x 004900 Reserved 0x00 49FF 0x00 5000 GPIO and peripheral registers(2) 0x00 57FF 0x00 5800 Reserved 0x00 7EFF 0x00 7F00 0x00 7FFF 0x00 8000 0x00 807F 0x00 8080 CPU/SWIM/Debug/ITC Registers Interrupt vectors 0x00 05FF 0x00 0600 Flash program memory (up to 8 Kbytes) (1) including Data EEPROM (up to 2 Kbytes) 0x00 9FFF 1. Table 5 lists the boundary addresses for each memory size. The top of the stack is at the RAM end address. 2. Refer to Table 7 for an overview of hardware register mapping, to Table 6 for details on I/O port hardware registers, and to Table 8 for information on CPU/SWIM/debug module controller registers. Doc ID 15275 Rev 7 23/77 Memory and register map Table 5. Flash and RAM boundary addresses Size 1.5 Kbytes 4 Kbytes Flash program memory 8 Kbytes 0x00 8000 Start Address 0x00 0000 0x00 8000 STM8L101xx Memory area RAM End address 0x00 05FF 0x00 8FFF 0x00 9FFF Table 6. Address 0x00 5000 0x00 5001 0x00 5002 0x00 5003 0x00 5004 0x00 5005 0x00 5006 0x00 5007 0x00 5008 0x00 5009 0x00 500A 0x00 500B 0x00 500C 0x00 500D 0x00 500E 0x00 500F 0x00 5010 0x00 5011 0x00 5012 0x00 5013 I/O Port hardware register map Block Register label PA_ODR PA_IDR Port A PA_DDR PA_CR1 PA_CR2 PB_ODR PB_IDR Port B PB_DDR PB_CR1 PB_CR2 PC_ODR PC_IDR Port C PC_DDR PC_CR1 PC_CR2 PD_ODR PD_IDR Port D PD_DDR PD_CR1 PD_CR2 Register name Port A data output latch register Port A input pin value register Port A data direction register Port A control register 1 Port A control register 2 Port B data output latch register Port B input pin value register Port B data direction register Port B control register 1 Port B control register 2 Port C data output latch register Port C input pin value register Port C data direction register Port C control register 1 Port C control register 2 Port D data output latch register Port D input pin value register Port D data direction register Port D control register 1 Port D control register 2 Reset status 0x00 0xxx 0x00 0x00 0x00 0x00 0xxx 0x00 0x00 0x00 0x00 0xxx 0x00 0x00 0x00 0x00 0xxx 0x00 0x00 0x00 24/77 Doc ID 15275 Rev 7 STM8L101xx Table 7. Address 0x00 5050 0x00 5051 0x00 5052 0x00 5053 0x00 5054 0x00 5065 to 0x00 509F 0x00 50A0 0x00 50A1 0x00 50A2 ITC-EXTI 0x00 50A3 0x00 50A4 0x00 50A5 0x00 50A6 WFE 0x00 50A7 0x00 50A8 to 0x00 50AF 0x00 50B0 RST 0x00 50B1 0x00 50B4 to 0x00 50BF 0x00 50C0 0x00 50C1 to 0x00 50C2 0x00 50C3 0x00 50C4 0x00 50C5 0x00 50C7 to 0x00 50DF CLK_CCOR CLK_CKDIVR RST_SR RST_CR WFE_CR2 EXTI_SR1 EXTI_SR2 EXTI_CONF WFE_CR1 EXTI_CR1 EXTI_CR2 EXTI_CR3 Flash Memory and register map General hardware register map Block Register label FLASH_CR1 FLASH_CR2 FLASH _PUKR FLASH _DUKR FLASH _IAPSR Register name Flash control register 1 Flash control register 2 Flash Program memory unprotection register Data EEPROM unprotection register Flash in-application programming status register Reserved area (59 bytes) External interrupt control register 1 External interrupt control register 2 External interrupt control register 3 External interrupt status register 1 External interrupt status register 2 External interrupt port select register WFE control register 1 WFE control register 2 Reserved area (8 bytes) Reset control register Reset status register Reserved area (12 bytes) Clock divider register Reserved area (2 bytes) CLK CLK_PCKENR Peripheral clock gating register Reserved (1 byte) Configurable clock control register Reserved area (18 bytes) 0x00 0x00 0x03 0x00 0x01 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 Reset status 0x00 0x00 0x00 0x00 0xX0 Doc ID 15275 Rev 7 25/77 Memory and register map Table 7. Address 0x00 50E0 0x00 50E1 0x00 50E2 0x00 50E3 to 0x00 50EF 0x00 50F0 0x00 50F1 0x00 50F2 0x00 50F3 0x00 50F4 to 0x00 50FF 0x00 5200 0x00 5201 0x00 5202 0x00 5203 0x00 5204 0x00 5205 to 0x00 520F 0x00 5210 0x00 5211 0x00 5212 0x00 5213 0x00 5214 0x00 5215 0x00 5216 I2C 0x00 5217 0x00 5218 0x00 5219 0x00 521A 0x00 521B 0x00 521C 0x00 521D I2C_SR1 I2C_SR2 I2C_SR3 I2C_ITR I2C_CCRL I2C_CCRH I2C_TRISER I2C status register 1 I2C status register 2 I2C status register 3 I2C interrupt control register I2C Clock control register low I2C Clock control register high I2C TRISE register I2C_DR I2C_CR1 I2C_CR2 I2C_FREQR I2C_OARL I2C_OARH SPI SPI_CR1 SPI_CR2 SPI_ICR SPI_SR SPI_DR BEEP AWU AWU_CSR AWU_APR AWU_TBR BEEP_CSR IWDG STM8L101xx General hardware register map (continued) Block Register label IWDG_KR IWDG_PR IWDG_RLR Register name IWDG Key register IWDG Prescaler register IWDG Reload register Reserved area (13 bytes) AWU control/status register AWU asynchronous prescaler buffer register AWU timebase selection register BEEP control/status register Reserved area (12 bytes) SPI control register 1 SPI control register 2 SPI interrupt control register SPI status register SPI data register Reserved area (11 bytes) I2C control register 1 I2C control register 2 I2C frequency register I2C Own address register low I2C Own address register high Reserved area (1 byte) I2C data register 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x02 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x02 0x00 0x00 0x3F 0x00 0x1F Reset status 0xXX 0x00 0xFF 26/77 Doc ID 15275 Rev 7 STM8L101xx Table 7. Address 0x00 521E to 0x00 522F 0x00 5230 0x00 5231 0x00 5232 0x00 5233 USART 0x00 5234 0x00 5235 0x00 5236 0x00 5237 0x00 523B to 0x00 524F USART_CR1 USART_CR2 USART_CR3 USART_CR4 USART_SR USART_DR USART_BRR1 USART_BRR2 Memory and register map General hardware register map (continued) Block Register label Register name Reset status Reserved area (18 bytes) USART Status Register USART Data Register USART Baud Rate Register 1 USART Baud Rate Register 2 USART Control Register 1 USART Control Register 2 USART Control Register 3 USART Control Register 4 Reserved area (21 bytes) 0xC0 0xXX 0x00 0x00 0x00 0x00 0x00 0x00 Doc ID 15275 Rev 7 27/77 Memory and register map Table 7. Address 0x00 5250 0x00 5251 0x00 5252 0x00 5253 0x00 5254 0x00 5255 0x00 5256 0x00 5257 0x00 5258 0x00 5259 0x00 525A TIM2 0x00 525B 0x00 525C 0x00 525D 0x00 525E 0x00 525F 0x00 5260 0x00 5261 0x00 5262 0x00 5263 0x00 5264 0x00 5265 0x00 5256 to 0x00 527F TIM2_CNTRH TIM2_CNTRL TIM2_PSCR TIM2_ARRH TIM2_ARRL TIM2_CCR1H TIM2_CCR1L TIM2_CCR2H TIM2_CCR2L TIM2_BKR TIM2_OISR TIM2 Counter high TIM2 Counter low TIM2 Prescaler register TIM2 Auto-reload register high TIM2 Auto-reload register low STM8L101xx General hardware register map (continued) Block Register label TIM2_CR1 TIM2_CR2 TIM2_SMCR TIM2_ETR TIM2_IER TIM2_SR1 TIM2_SR2 TIM2_EGR TIM2_CCMR1 TIM2_CCMR2 TIM2_CCER1 Register name TIM2 Control register 1 TIM2 Control register 2 TIM2 Slave Mode Control register TIM2 external trigger register TIM2 Interrupt enable register TIM2 Status register 1 TIM2 Status register 2 TIM2 Event Generation register TIM2 Capture/Compare mode register 1 TIM2 Capture/Compare mode register 2 TIM2 Capture/Compare enable register 1 Reset status 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0xFF 0xFF 0x00 0x00 0x00 0x00 0x00 0x00 TIM2 Capture/Compare register 1 high TIM2 Capture/Compare register 1 low TIM2 Capture/Compare register 2 high TIM2 Capture/Compare register 2 low TIM2 Break register TIM2 Output idle state register Reserved area (42 bytes) 28/77 Doc ID 15275 Rev 7 STM8L101xx Table 7. Address 0x00 5280 0x00 5281 0x00 5282 0x00 5283 0x00 5284 0x00 5285 0x00 5286 0x00 5287 0x00 5288 0x00 5289 0x00 528A TIM3 0x00 528B 0x00 528C 0x00 528D 0x00 528E 0x00 528F 0x00 5290 0x00 5291 0x00 5292 0x00 5293 0x00 5294 0x00 5295 0x00 5296 to 0x00 52DF 0x00 52E0 0x00 52E1 0x00 52E2 0x00 52E3 0x00 52E4 0x00 52E5 0x00 52E6 0x00 52E7 0x00 52E8 TIM4 TIM4_CR1 TIM4_CR2 TIM4_SMCR TIM4_IER TIM4_SR1 TIM4_EGR TIM4_CNTR TIM4_PSCR TIM4_ARR TIM3_CNTRH TIM3_CNTRL TIM3_PSCR TIM3_ARRH TIM3_ARRL TIM3_CCR1H TIM3_CCR1L TIM3_CCR2H TIM3_CCR2L TIM3_BKR TIM3_OISR Memory and register map General hardware register map (continued) Block Register label TIM3_CR1 TIM3_CR2 TIM3_SMCR TIM3_ETR TIM3_IER TIM3_SR1 TIM3_SR2 TIM3_EGR TIM3_CCMR1 TIM3_CCMR2 TIM3_CCER1 Register name TIM3 Control register 1 TIM3 Control register 2 TIM3 Slave Mode Control register TIM3 external trigger register TIM3 Interrupt enable register TIM3 Status register 1 TIM3 Status register 2 TIM3 Event Generation register TIM3 Capture/Compare mode register 1 TIM3 Capture/Compare mode register 2 TIM3 Capture/Compare enable register 1 TIM3 Counter high TIM3 Counter low TIM3 Prescaler register TIM3 Auto-reload register high TIM3 Auto-reload register low TIM3 Capture/Compare register 1 high TIM3 Capture/Compare register 1 low TIM3 Capture/Compare register 2 high TIM3 Capture/Compare register 2 low TIM3 Break register TIM3 Output idle state register Reserved area (74 bytes) TIM4 Control register 1 TIM4 Control register 2 TIM4 Slave Mode Control Register TIM4 Interrupt enable register TIM4 Status register 1 TIM4 Event Generation register TIM4 Counter TIM4 Prescaler register TIM4 Auto-reload register low 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0xFF Reset status 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0xFF 0xFF 0x00 0x00 0x00 0x00 0x00 0x00 Doc ID 15275 Rev 7 29/77 Memory and register map Table 7. Address 0x00 52E9 to 0x00 52FE 0x00 52FF 0x00 5300 0x00 5301 0x00 5302 COMP IR IR_CR COMP_CR COMP_CSR COMP_CCS STM8L101xx General hardware register map (continued) Block Register label Register name Reset status Reserved area (23 bytes) Infra-red control register Comparator control register Comparator status register Comparator channel selection register 0x00 0x00 0x00 0x00 Table 8. Address 0x00 7F00 0x00 7F01 0x00 7F02 0x00 7F03 0x00 7F04 0x00 7F05 0x00 7F06 0x00 7F07 0x00 7F08 0x00 7F09 0x00 7F0A 0x00 7F0B to 0x00 7F5F 0x00 7F60 0x00 7F61 0x00 7F6F 0x00 7F70 0x00 7F71 0x00 7F72 0x00 7F73 0x00 7F74 0x00 7F75 0x00 7F76 0x00 7F77 CPU/SWIM/debug module/interrupt controller registers Block Register label A PCE PCH PCL XH CPU XL YH YL SPH SPL CC Register name Accumulator Program counter extended Program counter high Program counter low X index register high X index register low Y index register high Y index register low Stack pointer high Stack pointer low Condition code register Reserved area (85 bytes) CFG CFG_GCR Global configuration register Reserved area (15 bytes) ITC_SPR1 ITC_SPR2 ITC_SPR3 ITC-SPR (1) Reset status 0x00 0x00 0x80 0x00 0x00 0x00 0x00 0x00 0x05 0xFF 0x28 0x00 Interrupt Software priority register 1 Interrupt Software priority register 2 Interrupt Software priority register 3 Interrupt Software priority register 4 Interrupt Software priority register 5 Interrupt Software priority register 6 Interrupt Software priority register 7 Interrupt Software priority register 8 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF ITC_SPR4 ITC_SPR5 ITC_SPR6 ITC_SPR7 ITC_SPR8 30/77 Doc ID 15275 Rev 7 STM8L101xx Table 8. Address 0x00 7F78 to 0x00 7F79 0x00 7F80 0x00 7F81 to 0x00 7F8F 0x00 7F90 0x00 7F91 0x00 7F92 0x00 7F93 0x00 7F94 0x00 7F95 0x00 7F96 0x00 7F97 0x00 7F98 0x00 7F99 0x00 7F9A DM DM_BK1RE DM_BK1RH DM_BK1RL DM_BK2RE DM_BK2RH DM_BK2RL DM_CR1 DM_CR2 DM_CSR1 DM_CSR2 DM_ENFCTR SWIM SWIM_CSR Memory and register map CPU/SWIM/debug module/interrupt controller registers (continued) Block Register label Register name Reset status Reserved area (2 bytes) SWIM control status register Reserved area (15 bytes) Breakpoint 1 register extended byte Breakpoint 1 register high byte Breakpoint 1 register low byte Breakpoint 2 register extended byte Breakpoint 2 register high byte Breakpoint 2 register low byte Debug module control register 1 Debug module control register 2 Debug module control/status register 1 Debug module control/status register 2 Enable function register 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0x00 0x00 0x10 0x00 0xFF 0x00 1. Refer to Table 7: General hardware register map on page 25 (addresses 0x00 50A0 to 0x00 50A5) for a list of external interrupt registers. Doc ID 15275 Rev 7 31/77 Interrupt vector mapping STM8L101xx 6 Table 9. IRQ No. Interrupt vector mapping Interrupt mapping Wakeup from Halt mode Yes Wakeup from Active-halt mode Yes Wakeup from Wait (WFI mode) Yes Wakeup from Wait (WFE mode) Yes Vector address 0x00 8000 0x00 8004 0x00 8008 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes(1) Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes (1) Source block RESET TRAP Reset Description Software interrupt Reserved 0 1 2-3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 2324 25 26 TIM4 SPI COMP TIM2 TIM2 TIM3 TIM3 EXTIB EXTID EXTI0 EXTI1 EXTI2 EXTI3 EXTI4 EXTI5 EXTI6 EXTI7 AWU FLASH EOP/WR_PG_DIS Reserved Auto wakeup from Halt Reserved External interrupt port B External interrupt port D External interrupt 0 External interrupt 1 External interrupt 2 External interrupt 3 External interrupt 4 External interrupt 5 External interrupt 6 External interrupt 7 Reserved Reserved Comparators Update /Overflow/Trigger/Break Capture/Compare Update /Overflow/Break Capture/Compare Reserved Update /Trigger End of Transfer 0x00 800C 0x00 8010 -0x00 8017 0x00 8018 0x00 801C 0x00 8020 0x00 8024 0x00 8028 0x00 802C 0x00 8030 0x00 8034 0x00 8038 0x00 803C 0x00 8040 0x00 8044 0x00 8048 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes(1) Yes Yes Yes(1) Yes Yes(1) Yes(1) (1) 0x00 804C -0x00 804F 0x00 8050 0x00 8054 0x00 8058 0x00 805C 0x00 8060 0x00 80640x00 806B 0x00 806C 0x00 8070 32/77 Doc ID 15275 Rev 7 STM8L101xx Table 9. IRQ No. Interrupt vector mapping Interrupt mapping (continued) Wakeup from Halt mode Wakeup from Active-halt mode Wakeup from Wait (WFI mode) Yes Wakeup from Wait (WFE mode) Yes(1) Vector address Source block Description 27 USART Transmission complete/transmit data register empty Receive Register DATA FULL/overrun/idle line detected/parity error I2C interrupt(2) - 0x00 8074 28 29 USART I2C Yes Yes Yes Yes Yes(1) Yes(1) 0x00 8078 0x00 807C 1. In WFE mode, this interrupt is served if it has been previously enabled. After processing the interrupt, the processor goes back to WFE mode. Section : Wait for event (WFE) mode on page 70. 2. The device is woken up from Halt or Active-halt mode only when the address received matches the interface address. Doc ID 15275 Rev 7 33/77 Option bytes STM8L101xx 7 Option bytes Option Bytes contain configurations for device hardware features as well as the memory protection of the device. They are stored in a dedicated row of the memory. All option bytes can be modified only in ICP mode (with SWIM) by accessing the EEPROM address. See Table 10 for details on option byte addresses. Refer to the STM8L Flash programming manual (PM0054) and STM8 SWIM and Debug Manual (UM0320) for information on SWIM programming procedures. Table 10. Addr. Option bytes Option name Read-out protection (ROP) Option byte No. OPT1 OPT2 OPT3 OPT4 [1:0] Option bits 7 6 5 4 3 ROP[7:0] Must be programmed to 0x00 UBC[7:0] DATASIZE[7:0] Reserved IWDG _HALT IWDG _HW 2 1 0 Factory default setting 0x00 0x00 0x00 0x00 0x00 0x4800 0x4807 0x4802 0x4803 0x4808 UBC(User Boot code size) DATASIZE Independent watchdog option Table 11. OPT1 Option byte description ROP[7:0] Memory readout protection (ROP) 0xAA: Enable Readout protection (write access via SWIM protocol) Refer to Read-out protection section in the STM8L reference manual (RM0013) for details. UBC[7:0] Size of the user boot code area 0x00: no UBC 0x01-0x02: UBC contains only the interrupt vectors. 0x03: Page 0 and 1 reserved for the interrupt vectors. Page 2 is available to store user boot code. Memory is write protected ... 0x7F - Page 0 to 126 reserved for UBC, memory is write protected Refer to User boot area (UBC) section in the STM8L reference manual (RM0013) for more details. DATASIZE[7:0] Size of the data EEPROM area 0x00: no data EEPROM area (1) 0x01 - 1 page reserved for data storage.(1) ... (1) 0x20 - 32 pages reserved for data storage.(1) Refer to Data EEPROM (DATA) section in the STM8L reference manual (RM0013) for more details. OPT2 OPT3 34/77 Doc ID 15275 Rev 7 STM8L101xx Table 11. Option byte description (continued) IWDG_HW: Independent watchdog 0: Independent watchdog activated by software 1: Independent watchdog activated by hardware OPT4 Option bytes IWDG_HALT: Independent window watchdog reset on Halt/Active-halt 0: Independent watchdog continues running in Halt/Active-halt mode 1: Independent watchdog stopped in Halt/Active-halt mode 1. 0x00 is the only allowed value for 4 Kbyte STM8L101xx devices. Caution: After a device reset, read access to the program memory is not guaranteed if address 0x4807 is not programmed to 0x00. Doc ID 15275 Rev 7 35/77 Unique ID STM8L101xx 8 Unique ID devices feature a 96-bit unique device identifier which provides a reference number that is unique for any device and in any context. The 96 bits of the identifier can never be altered by the user. The unique device identifier can be read in single bytes and may then be concatenated using a custom algorithm. The unique device identifier is ideally suited: For use as serial numbers For use as security keys to increase the code security in the program memory while using and combining this unique ID with software crytograhic primitives and protocols before programming the internal memory. To activate secure boot processes Unique ID registers (96 bits) Content description X co-ordinate on the wafer Y co-ordinate on the wafer Wafer number Unique ID bits 7 6 5 4 3 U_ID[7:0] U_ID[15:8] U_ID[23:16] U_ID[31:24] U_ID[39:32] U_ID[47:40] U_ID[55:48] U_ID[63:56] Lot number U_ID[71:64] U_ID[79:72] U_ID[87:80] U_ID[95:88] 2 1 0 Table 12. Address 0x4925 0x4926 0x4927 0x4928 0x4929 0x492A 0x492B 0x492C 0x492D 0x492E 0x492F 0x4930 36/77 Doc ID 15275 Rev 7 STM8L101xx Electrical parameters 9 9.1 Electrical parameters Parameter conditions Unless otherwise specified, all voltages are referred to VSS. 9.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA= 25 C and TA = TA max (given by the selected temperature range). Note: The values given at 85 C Typical values Unless otherwise specified, typical data are based on TA = 25 C, VDD = 3 V. They are given only as design guidelines and are not tested. 9.1.3 Typical curves Unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 9.1.4 Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 9. Figure 9. Pin loading conditions STM8L PIN 50 pF Doc ID 15275 Rev 7 37/77 Electrical parameters STM8L101xx 9.1.5 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 10. Figure 10. Pin input voltage STM8L PIN VIN 9.2 Absolute maximum ratings Stresses above those listed as "absolute maximum ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 13. Symbol VDD- VSS VIN Voltage characteristics Ratings External supply voltage Input voltage on true open drain pins (PC0 and PC1) Input voltage on any other pin (1) Min -0.3 VSS-0.3 VSS-0.3 Max 4.0 5.25 4.6 V Unit VESD Electrostatic discharge voltage see Absolute maximum ratings (electrical sensitivity) on page 62 1. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN Doc ID 15275 Rev 7 STM8L101xx Table 14. Symbol IVDD IVSS Electrical parameters Current characteristics Ratings Total current into VDD power line (source) Total current out of VSS ground line (sink) Output current sunk by IR_TIM pin (with high sink LED driver capability) IIO Output current sunk by any other I/O and control pin Output current source by any I/Os and control pin IINJ(PIN) (1) (1) Max. 80 80 80 25 -25 5 (2) Unit mA Injected current on any pin (2) IINJ(PIN) Total injected current (sum of all I/O and control pins) 25 1. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN Symbol TSTG TJ Thermal characteristics Ratings Storage temperature range Maximum junction temperature Min -65 to +150 C 150 Unit Doc ID 15275 Rev 7 39/77 Electrical parameters STM8L101xx 9.3 Operating conditions Subject to general operating conditions for VDD, and TA. 9.3.1 Table 16. Symbol fMASTER(1) VDD General operating conditions General operating conditions Parameter Master clock frequency Standard operating voltage LQFP32 WFQFPN32 Power dissipation at TA= 85 C for suffix 6 devices WFQFPN28 TSSOP20 Conditions 1.65 V VDD < 3.6 V Min 2 1.65 - 40 - 40 - 40 - 40 Max 16 3.6 288 288 286 181 196 mW LQFP32 WFQFPN32 Power dissipation at TA= 125 C for suffix 3 devices WFQFPN28 TSSOP20 UFQFPN20 1.65 V VDD < 3.6 V (6 suffix version) 83 227 71 45 49 85 C 125 105 130 C C Unit MHz V PD(2) UFQFPN20 TA Temperature range 1.65 V VDD < 3.6 V (3 suffix version) -40 C TA 85 C (6 suffix version) TJ Junction temperature range -40 C TA 125 C (3 suffix version) 1. fMASTER = fCPU 2. To calculate PDmax(TA) use the formula given in thermal characteristics PDmax=(TJmax -TA)/ with TJmax in this table and JA JA in table "Thermal characteristics" 40/77 Doc ID 15275 Rev 7 STM8L101xx Electrical parameters 9.3.2 Power-up / power-down operating conditions Table 17. Symbol tVDD tTEMP VPOR(1) VPDR(1) Operating conditions at power-up / power-down Parameter VDD rise time rate Reset release delay Power on reset threshold Power down reset threshold VDD rising Conditions Min 20 1.35 1.40 Typ 1 Max 1300 TBD 1.65(2) 1.60 Unit s/V ms V V 1. Data based on characterization results, not tested in production. 2. Data guaranteed, each individual device tested in production. 9.3.3 Supply current characteristics Total current consumption The MCU is placed under the following conditions: All I/O pins in input mode with a static value at VDD or VSS (no load) All peripherals are disabled except if explicitly mentioned. Subject to general operating conditions for VDD and TA. Figure 11. IDD(RUN) vs. VDD@ fCPU = 2 MHz @4 temperatures 1 0.9 0.8 0.7 IDD(RUN)HSI [mA] 0.6 0.5 0.4 0.3 0.2 0.1 0 1.6 1.7 1.8 1.9 2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.6 VDD [V] IDD(RUN)HSI [mA] Figure 12. IDD(RUN) vs. VDD@ fCPU = 16 MHz @4 temperatures 3 2.9 2.8 2.7 2.6 2.5 2.4 2.3 2.2 2.1 2 1.6 1.7 1.8 1.9 2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.6 VDD [V] -40C 25C 85C 125C -40C 25C 85C 125C ai17017 ai17018 1. Typical current consumption measured with code executed from Flash. Doc ID 15275 Rev 7 41/77 Electrical parameters Table 18. Total current consumption in Run mode (1) Conditions(2) fMASTER = 2 MHz Code executed from RAM Supply current in IDD (Run) Run mode(4) Code executed from Flash fMASTER = 4 MHz fMASTER = 8 MHz fMASTER = 16 MHz fMASTER = 2 MHz fMASTER = 4 MHz fMASTER = 8 MHz fMASTER = 16 MHz 1. Based on characterization results, unless otherwise specified. 2. All peripherals off, VDD from 1.65 V to 3.6 V, HSI internal RC osc. , fCPU=fMASTER 3. Maximum values are given for TA = - 40 to 125 C. 4. CPU executing typical data processing. 5. Data guaranteed, each individual device tested in production. STM8L101xx Symbol Parameter Typ 0.39 0.55 0.9 1.6 0.55 0.88 1.5 2.7 Max(3) 0.6 0.7 1.2 2.1(5) Unit mA 0.7 1.8 2.5 3.5 Table 19. Symbol Total current consumption in Wait mode(1) Parameter Conditions fMASTER = 2 MHz Typ 245 300 380 510 Max(2) 400 450 A 600 800 Unit IDD (Wait) Supply current in Wait mode CPU not clocked, all peripherals off, HSI internal RC osc. fMASTER = 4 MHz fMASTER = 8 MHz fMASTER = 16 MHz 1. Based on characterization results, unless otherwise specified. 2. Maximum values are given for TA = -40 to 125 C. Figure 13. IDD(WAIT) vs. VDD@ fCPU = 2 MHz @4 temperatures 300 Figure 14. IDD(WAIT) vs. VDD@ fCPU = 16 MHz @4 temperatures 600 550 250 500 IDD(RUN)HSI [A] IDD(WFI)HSI [A] 200 150 100 50 0 -40C 25C 85C 125C 450 400 350 300 250 -40C 25C 85C 125C 1.6 1.7 1.8 1.9 2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.6 VDD [V] 200 1.6 2.1 2.6 VDD [V] 3.1 3.6 ai17015 ai17016 1. Typical current consumption measured with code executed from Flash. 42/77 Doc ID 15275 Rev 7 STM8L101xx Table 20. Symbol Electrical parameters Total current consumption and timing in Halt and Active-halt mode at VDD = 1.65 V to 3.6 V (1)(2) Parameter Conditions TA = -40 C to 25 C TA = 55 C IDD(AH) Supply current in Active-halt mode LSI RC osc. (at 37 kHz) TA = 85 C TA = 105 C TA = 125 C Supply current during IDD(WUFAH) wakeup time from Active-halt mode tWU(AH)(3) Wakeup time from Activehalt mode to run mode fCPU= 16 MHz TA = -40 C to 25 C TA = 55 C IDD(Halt) Supply current in Halt mode TA = 85 C TA = 105 C TA = 125 C IDD(WUFH) tWU(Halt)(3) Supply current during wakeup time from Halt mode Wakeup time from Halt mode fCPU = 16 MHz to run mode Typ 0.8 1 1.4 2.9 5.8 2 Max 2 2.5 3.2 7.5 13 Unit A A A A A mA 4 0.35 0.6 1 2.5 5.4 2 4 6.5 1.2(4) 1.8 2.5(4) 6.5 12(4) 6.5 s A A A A A mA s 1. TA = -40 to 125 C, no floating I/O, unless otherwise specified. 2. Data based on characterization results, not tested in production. 3. Measured from interrupt event to interrupt vector fetch. To get tWU for another CPU frequency use tWU(FREQ) = tWU(16 MHz) + 1.5 (TFREQ-T16 MHz). The first word of interrupt routine is fetched 5 CPU cycles after tWU. 4. Data guaranteed, each individual device tested in production. Figure 15. Typ. IDD(Halt) vs. VDD @ fCPU = 2 MHz and 16 MHz @4 temperatures 7 6 -40C 5 IDD(HALT) [A] 4 3 2 1 0 1.6 2.1 2.6 VDD [V] 3.1 3.6 25C 85C 125C ai17014b 1. Typical current consumption measured with code executed from Flash. Doc ID 15275 Rev 7 43/77 Electrical parameters STM8L101xx Current consumption of on-chip peripherals Measurement made for fMASTER = from 2 MHz to 16 MHz Table 21. Symbol IDD(TIM2) IDD(TIM3) IDD(TIM4) IDD(USART) IDD(SPI) IDD(IC1) IDD(COMP) Peripheral current consumption Parameter TIM2 supply current (1) Typ. VDD = 3.0 V 9 9 Unit TIM3 supply current (1) TIM4 timer supply current USARTsupply current SPI supply current (2) I2C supply current (2) Comparator supply current (2) (2) (1) 4 A/MHz 7 4 4 20 A 1. Data based on a differential IDD measurement between all peripherals off and a timer counter running at 16 MHz. The CPU is in Wait mode in both cases. No IC/OC programmed, no I/O pin toggling. Not tested in production. 2. Data based on a differential IDD measurement between the on-chip peripheral when kept under reset and not clocked and the on-chip peripheral when clocked and not kept under reset. The CPU is in Wait mode in both cases. No I/O pin toggling. Not tested in production. 44/77 Doc ID 15275 Rev 7 STM8L101xx Electrical parameters 9.3.4 Clock and timing characteristics Internal clock sources Subject to general operating conditions for VDD, and TA. High speed internal RC oscillator (HSI) Table 22. Symbol fHSI HSI oscillator characteristics (1) Parameter Frequency Conditions VDD = 3.0 V VDD = 3.0 V, TA = 25 C VDD = 3.0 V, -10 C TA 85 C VDD = 3.0 V, -10 C TA 125 C VDD = 3.0 V, 0 C TA 55 C VDD = 3.0 V, -10 C TA 70 C 1.65 V VDD 3.6 V, -40 C TA 125 C Min -1 (2) Typ 16 Max 1 (2) Unit MHz % % % % % % A -2.5(2) -4.5(2) -1.5(2)(3) -2(2)(3) -4.5(3) 70 2(2) 2(2) 1.5(2)(3) 2(2)(3) 3(3) 100(3) ACCHSI Accuracy of HSI oscillator (factory calibrated) IDD(HSI) HSI oscillator power consumption 1. VDD = 3.0 V, TA = -40 to 125 C unless otherwise specified. 2. Further characterization results expected. 3. Data based on characterization results, not tested in production. Figure 16. Typical HSI frequency vs VDD @ 4 temperatures 17 16.8 16.6 HSI frequency [MHz] 16.4 16.2 16 15.8 15.6 15.4 15.2 15 1.65 1.8 1.95 2.1 2.25 2.4 2.55 2.7 2.85 VDD [V] 3 3.15 3.3 3.45 3.6 -40C 25C 85C 125C ai17013 Doc ID 15275 Rev 7 45/77 Electrical parameters Figure 17. Typical HSI accuracy at VDD = 3 V vs temperature 3.5% 3.0% 2.5% 2.0% 1.5% 1.0% 0.5% 0.0% RC accuracy STM8L101xx 3V min 3V typical 3V max -0.5% -1.0% -1.5% -2.0% -2.5% -3.0% -3.5% -4.0% -4.5% -5.0% -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 Temperature (C) ai17021 Figure 18. Typical HSI accuracy at VDD = 1.65 V to 3.6 V vs temperature 3.5% 3.0% 2.5% 2.0% 1.5% 1.0% 0.5% 0.0% RC accuracy Min 1.65V-3.6V Max 1.65V-3.6V 3V typical -0.5% -1.0% -1.5% -2.0% -2.5% -3.0% -3.5% -4.0% -4.5% -5.0% -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 Temperature (C) ai17019 Low speed internal RC oscillator (LSI) Table 23. Symbol fLSI tsu(LSI) fdrift(LSI) LSI oscillator characteristics (1) Parameter Frequency LSI oscillator wakeup time LSI oscillator frequency drift(2) 0 C TA 85C Conditions Min 26 -12 Typ 38 TBD Max 56 11 Unit kHz s % 1. VDD = 1.65 V to 3.6 V, TA = -40 to 125 C unless otherwise specified. 2. For each individual part, this value is the frequency drift from the initial measured frequency. 46/77 Doc ID 15275 Rev 7 STM8L101xx Figure 19. Typical LSI RC frequency vs. VDD @ 4 temperatures 45 43 41 LSI frequency [MHz] 39 37 35 33 31 29 27 25 1.6 2.1 2.6 VDD [V] 3.1 3.6 Electrical parameters -40C 25C 85C 125C ai17012b Doc ID 15275 Rev 7 47/77 Electrical parameters STM8L101xx 9.3.5 Memory characteristics TA = -40 to 125 C unless otherwise specified. Table 24. Symbol VRM RAM and hardware registers Parameter Data retention mode (1) Conditions Halt mode (or Reset) Min 1.4 Typ Max Unit V 1. Minimum supply voltage without losing data stored in RAM (in Halt mode or under Reset) or in hardware registers (only in Halt mode). Guaranteed by characterization, not tested in production. Flash memory Table 25. Symbol VDD Flash program memory Parameter Operating voltage (all modes, read/write/erase) Programming time for 1 or 64 bytes (block) erase/write cycles (on programmed byte) Conditions fMASTER = 16 MHz Min 1.65 TA=+25 C, VDD = 3.0 V TA=+25 C, VDD = 1.8 V TRET = 55 C 0.7 20(1) Typ Max (1) Unit V ms ms 3.6 6 3 - tprog Programming time for 1 to 64 bytes (block) write cycles (on erased byte) Programming/ erasing consumption Data retention (program memory) after 10k erase/write cycles at TA = +85 C Iprog mA tRET Data retention (data memory) after 10k erase/write cycles at TA = +85 C Data retention (data memory) after 300k erase/write cycles at TA = +125 C Erase/write cycles (program memory) TRET = 55 C 20(1) - - years TRET = 85 C See notes (1)(2) See notes (1)(3) 1(1) 10(1) 300(1)(4) - kcycles - NRW Erase/write cycles (data memory) 1. Data based on characterization results, not tested in production. 2. Retention guaranteed after cycling is 10 years @ 55 C. 3. Retention guaranteed after cycling is 1 year @ 55 C. 4. Data based on characterization performed on the whole data memory (2 Kbytes). 48/77 Doc ID 15275 Rev 7 STM8L101xx Electrical parameters 9.3.6 I/O port pin characteristics General characteristics Subject to general operating conditions for VDD and TA unless otherwise specified. All unused pins must be kept at a fixed voltage: using the output mode of the I/O for example or an external pull-up or pull-down resistor. Table 26. Symbol VIL I/O static characteristics (1) Parameter Input low level voltage(2) Conditions Standard I/Os True open drain I/Os Input high level voltage (2) Standard I/Os True open drain I/Os Schmitt trigger voltage hysteresis (3) Standard I/Os True open drain I/Os VSSVINVDD Standard I/Os Min VSS-0.3 VSS-0.3 0.70 x VDD 0.70 x VDD Typ 200 250 Max 0.3 x VDD 0.3 x VDD VDD+0.3 5.25 mV 50 (5) 200(5) V Unit V VIH Vhys Ilkg Input leakage current (4) VSSVINVDD True open drain I/Os VSSVINVDD PA0 with high sink LED driver capability nA 30 - 45 5 200(5) 60 k pF RPU CIO (7) Weak pull-up equivalent resistor(6) I/O pin capacitance VIN=VSS 1. VDD = 3.0 V, TA = -40 to 85 C unless otherwise specified. 2. Data based on characterization results, not tested in production. 3. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested. 4. The max. value may be exceeded if negative current is injected on adjacent pins. 5. Not tested in production. 6. RPU pull-up equivalent resistor based on a resistive transistor (corresponding IPU current characteristics described in Figure 22). 7. Data guaranteed by Design, not tested in production. Doc ID 15275 Rev 7 49/77 Electrical parameters Figure 20. Typical VIL and VIH vs VDD (standard I/Os) 3 3 STM8L101xx 2.5 2.5 VIL and VIH [V] VIL and VIH [V] 2 2 -40C -40C 25C 25C 85C 85C 125C 125C 1.5 1.5 1 1 0.5 0.5 0 0 1.6 1.6 2.1 2.1 2.6 2.6 VDD [V] VDD [V] 3.1 3.1 3.6 3.6 ai17011 Figure 21. Typical VIL and VIH vs VDD (true open drain I/Os) 3 2.5 2 -40C 25C 85C 125C VIL and VIH [V] 1.5 1 0.5 0 1.6 2.1 2.6 VDD [V] 3.1 3.6 ai17010 Figure 22. Typical pull-up resistance RPU vs VDD @ 4 temperatures with VIN=VSS 60 55 Pull-Up resistance [k ] 50 45 40 35 30 1.65 1.8 1.95 2.1 2.25 2.4 2.55 2.7 2.85 VDD [V] -40C 25C 85C 125C 3 3.15 3.3 3.45 3.6 ai17009 50/77 Doc ID 15275 Rev 7 STM8L101xx Electrical parameters Figure 23. Typical pull-up current Ipu vs VDD @ 4 temperatures with VIN=VSS 120 100 -40C 25C 85C 125C Pull-Up current [A] 80 60 40 20 0 1.65 1.8 1.95 2.1 2.25 2.4 2.55 2.7 2.85 VDD [V] 3 3.15 3.3 3.45 3.6 ai17008 Doc ID 15275 Rev 7 51/77 Electrical parameters STM8L101xx Output driving current Subject to general operating conditions for VDD and TA unless otherwise specified. Table 27. Output driving current (standard ports) Parameter Conditions IIO = +2 mA, VDD = 3.0 V VOL (1) Standard Output low level voltage for an I/O pin IIO = +2 mA, VDD = 1.8 V IIO = +10 mA, VDD = 3.0 V IIO = -2 mA, VDD = 3.0 V VOH (2) Output high level voltage for an I/O pin IIO = -1 mA, VDD = 1.8 V IIO = -10 mA, VDD = 3.0 V Min VDD-0.45 VDD-0.45 VDD-1.2 Max 0.45 0.45 1.2 Unit V V V V V V I/O Symbol Type 1. The IIO current sunk must always respect the absolute maximum rating specified in Table 14 and the sum of IIO (I/O ports and control pins) must not exceed IVSS. 2. The IIO current sourced must always respect the absolute maximum rating specified in Table 14 and the sum of IIO (I/O ports and control pins) must not exceed IVDD. Table 28. Output driving current (true open drain ports) Parameter Conditions IIO = +3 mA, VDD = 3.0 V IIO = +1 mA, VDD = 1.8 V Min Max 0.45 0.45 Unit V V I/O Symbol Type Open drain VOL (1) Output low level voltage for an I/O pin 1. The IIO current sunk must always respect the absolute maximum rating specified in Table 14 and the sum of IIO (I/O ports and control pins) must not exceed IVSS. Table 29. Output driving current (PA0 with high sink LED driver capability) Parameter Output low level voltage for an I/O pin Conditions IIO = +20 mA, VDD = 2.0 V Min Max 0.9 Unit V I/O Symbol Type VOL (1) IR 52/77 1. The IIO current sunk must always respect the absolute maximum rating specified in Table 14 and the sum of IIO (I/O ports and control pins) must not exceed IVSS. Doc ID 15275 Rev 7 STM8L101xx Electrical parameters Figure 24. Typ. VOL @ VDD = 3.0 V (standard ports) 1.5 1.25 1 0.75 0.5 0.25 0 0 5 10 IOL [mA] 15 20 25 Figure 25. Typ. VOL @ VDD = 1.8 V (standard ports) 0.5 -40C 25C 85C 125C -40C 25C 85C 125C VOL [V] 0.4 0.3 0.2 0.1 BD T 0 1 2 3 IOL [mA] 4 5 6 7 0 ai17005 ai17004 Figure 26. Typ. VOL @ VDD = 3.0 V (true open drain ports) 0.5 Figure 27. Typ. VOL @ VDD = 1.8 V (true open drain ports) 0.5 -40C 0.4 25C 85C 125C VOL [V] 0.4 -40C 25C 85C 125C 0.3 VOL [V] 0.3 0.2 0.2 0.1 0.1 BD T 1 1.5 IOL [mA] 2 2.5 3 0 0 1 2 3 IOL [mA] 4 5 6 0 0 0.5 ai17003 ai17002 Figure 28. Typ. VDD - VOH @ VDD = 3.0 V (standard ports) 2 Figure 29. Typ. VDD - VOH @ VDD = 1.8 V (standard ports) 0.4 -40C 25C 85C 1.75 1.5 VDD - VOH [V] 1.25 1 0.75 0.5 -40C 25C 85C VDD - VOH [V] 0.3 125C 125C 0.2 0.1 0.25 0 0 2 4 6 8 10 12 IOH [mA] 14 16 18 20 22 24 0 0 1 2 3 IOH [mA] 4 5 6 ai17001 Doc ID 15275 Rev 7 53/77 Electrical parameters STM8L101xx NRST pin The NRST pin input driver is CMOS. A permanent pull-up is present which is the same as as RPU (see Table 26 on page 49) Subject to general operating conditions for VDD and TA unless otherwise specified. Table 30. Symbol VIL(NRST) VIH(NRST) VOL(NRST) RPU(NRST) VF(NRST) tOP(NRST) VNF(NRST) NRST pin characteristics Parameter NRST input low level voltage (1) NRST input high level voltage NRST output low level voltage NRST pull-up equivalent resistor (2) NRST input filtered pulse NRST output pulse width NRST input not filtered pulse (3) (3) (1) Conditions Min VSS 1.4 Typ (1) 45 - Max 0.8 VDD VDD-0.8 60 50 - Unit V IOL = 2 mA 30 20 300 k ns ns 1. Data based on characterization results, not tested in production. 2. The RPU pull-up equivalent resistor is based on a resistive transistor (Figure 30). Corresponding IPU current characteristics are described in Figure 31. 3. Data guaranteed by design, not tested in production. Figure 30. Typical NRST pull-up resistance RPU vs VDD @ 4 temperatures 60 55 -40C 25C 85C 125C Pull-Up resistance [k ] 50 45 40 35 30 1.65 1.8 1.95 2.1 2.25 2.4 2.55 2.7 2.85 VDD [V] 3 3.15 3.3 3.45 3.6 ai17007 54/77 Doc ID 15275 Rev 7 STM8L101xx Electrical parameters Figure 31. Typical NRST pull-up current Ipu vs VDD @ 4 temperatures 120 100 -40C 25C 85C 125C Pull-Up current [A] 80 60 40 20 0 1.65 1.8 1.95 2.1 2.25 2.4 2.55 2.7 2.85 VDD [V] 3 3.15 3.3 3.45 3.6 ai17006 The reset network shown in Figure 32 protects the device against parasitic resets. The user must ensure that the level on the NRST pin can go below the VIL max. level specified in Table 30. Otherwise the reset is not taken into account internally. Figure 32. Recommended NRST pin configuration VDD RPU EXTERNAL RESET CIRCUIT 0.01F RSTIN Filter INTERNAL RESET STM8L Doc ID 15275 Rev 7 55/77 Electrical parameters STM8L101xx 9.3.7 Communication interfaces Serial peripheral interface (SPI) Unless otherwise specified, the parameters given in Table 31 are derived from tests performed under ambient temperature, fMASTER frequency and VDD supply voltage conditions summarized in Section 9.3.1. Refer to I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO). Table 31. Symbol fSCK 1/tc(SCK) tr(SCK) tf(SCK) tsu(NSS)(2) th(NSS) (2) (2) SPI characteristics Parameter SPI clock frequency Slave mode SPI clock rise and fall time Capacitive load: C = 30 pF NSS setup time NSS hold time SCK high and low time Slave mode Slave mode Master mode, fMASTER = 8 MHz, fSCK= 4 MHz Master mode Data input setup time Slave mode Master mode Data input hold time Slave mode Data output access time Data output disable time Data output valid time Data output valid time Slave mode Slave mode Slave mode (after enable edge) Master mode (after enable edge) Slave mode (after enable edge) Data output hold time Master mode (after enable edge) 0 30 15 1 3x TMASTER 60 20 3 15 0 4 x TMASTER 80 105 30 8 30 145 Conditions(1) Master mode Min 0 Max 8 MHz Unit ns tw(SCKH) tw(SCKL)(2) tsu(MI) (2) tsu(SI)(2) th(MI) (2) th(SI)(2) ta(SO)(2)(3) tdis(SO)(2)(4) tv(SO) (2) tv(MO)(2) th(SO)(2) th(MO)(2) 1. Parameters are given by selecting 10 MHz I/O output frequency. 2. Values based on design simulation and/or characterization results, and not tested in production. 3. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data. 4. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z. 56/77 Doc ID 15275 Rev 7 STM8L101xx Figure 33. SPI timing diagram - slave mode and CPHA = 0 Electrical parameters NSS input tSU(NSS) SCK Input tc(SCK) th(NSS) CPHA= 0 CPOL=0 CPHA= 0 CPOL=1 tw(SCKH) tw(SCKL) tv(SO) MS B O UT tsu(SI) tr(SCK) tf(SCK) LSB OUT ta(SO) MISO OUT P UT MOSI I NPUT th(SO) BI T6 OUT tdis(SO) M SB IN th(SI) B I T1 IN LSB IN ai14134 Figure 34. SPI timing diagram - slave mode and CPHA = 1(1) NSS input tSU(NSS) SCK Input CPHA=1 CPOL=0 CPHA=1 CPOL=1 tc(SCK) th(NSS) tw(SCKH) tw(SCKL) tr(SCK) tf(SCK) ta(SO) MISO OUT P UT tsu(SI) MOSI I NPUT M SB IN tv(SO) MS B O UT th(SI) th(SO) BI T6 OUT tdis(SO) LSB OUT B I T1 IN LSB IN ai14135 1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD. Doc ID 15275 Rev 7 57/77 Electrical parameters Figure 35. SPI timing diagram - master mode(1) High NSS input tc(SCK) SCK Input CPHA= 0 CPOL=0 CPHA= 0 CPOL=1 STM8L101xx SCK Input CPHA=1 CPOL=0 CPHA=1 CPOL=1 tsu(MI) MISO INP UT MOSI OUTUT tw(SCKH) tw(SCKL) MS BIN th(MI) M SB OUT tv(MO) B I T1 OUT th(MO) ai14136 tr(SCK) tf(SCK) BI T6 IN LSB IN LSB OUT 1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD. 58/77 Doc ID 15275 Rev 7 STM8L101xx Electrical parameters Inter IC control interface (I2C) Subject to general operating conditions for VDD, fMASTER, and TA unless otherwise specified. The STM8L I2C interface meets the requirements of the Standard I2C communication protocol described in the following table with the restriction mentioned below: Refer to I/O port characteristics for more details on the input/output alternate function characteristics (SDA and SCL). Table 32. Symbol I2C characteristics Parameter Standard mode I2C Min(2) Max 1000 300 400 (2) Fast mode I2C(1) Unit Min (2) Max - (2) tw(SCLL) tw(SCLH) tsu(SDA) th(SDA) tr(SDA) tr(SCL) tf(SDA) tf(SCL) th(STA) tsu(STA) tsu(STO) tw(STO:STA) Cb SCL clock low time SCL clock high time SDA setup time SDA data hold time SDA and SCL rise time SDA and SCL fall time START condition hold time Repeated START condition setup time STOP condition setup time STOP to START condition time (bus free) Capacitive load for each bus line I 2C 4.7 4.0 250 0 (3) 1.3 0.6 100 0 (4) s 900 (3) 300 300 400 s s s pF ns 4.0 4.7 4.0 4.7 - 0.6 0.6 0.6 1.3 - 1. fSCK must be at least 8 MHz to achieve max fast speed (400 kHz). 2. Data based on standard I2C protocol requirement, not tested in production. 3. The maximum hold time of the START condition has only to be met if the interface does not stretch the low period of SCL signal. 4. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL). Note: For speeds around 200 kHz, achieved speed can have 5% tolerance For other speed ranges, achieved speed can have 2% tolerance The above variations depend on the accuracy of the external components used. Doc ID 15275 Rev 7 59/77 Electrical parameters Figure 36. Typical application with I2C bus and timing diagram 1) VDD 4.7k I 2C STM8L101xx VDD 4.7k 100 100 SDA SCL BUS STM8L REPEATED START START tsu(STA) SDA tw(STO:STA) START tf(SDA) SCL tr(SDA) tsu(SDA) th(SDA) STOP th(STA) tw(SCKH) tw(SCKL) tr(SCK) tf(SCK) tsu(STO) 1. Measurement points are done at CMOS levels: 0.3 x VDD and 0.7 x VDD 9.3.8 Table 33. Symbol Comparator characteristics Comparator characteristics Parameter Comparator external reference Comparator input voltage range Comparator offset error Startup time (after BIAS_EN) Analog comparator consumption Conditions Min (1) -0.1 -0.25 100 mV input step with 5 mV overdrive, input rise time = 1 ns Typ Max(1) VDD-1.25 VDD+0.25 20 3(1) 25(1) 60(1) Unit V V mV s A nA VIN(COMP_REF) VIN Voffset(2) tSTART IDD(COMP) Analog comparator consumption during power-down Comparator propagation delay tpropag(2) - - 2(1) s 1. Data guaranteed by design, not tested in production. 2. The comparator accuracy depends on the environment. In particular, the following cases may reduce the accuracy of the comparator and must be avoided: - Negative injection current on the I/Os close to the comparator inputs - Switching on I/Os close to the comparator inputs - Negative injection current on not used comparator input. - Switching with a high dV/dt on not used comparator input. These phenomena are even more critical when a big external serial resistor is added on the inputs. 60/77 Doc ID 15275 Rev 7 STM8L101xx Electrical parameters 9.3.9 EMC characteristics Susceptibility tests are performed on a sample basis during product characterization. Functional EMS (electromagnetic susceptibility) Based on a simple running application on the product (toggling 2 LEDs through I/O ports), the product is stressed by two electromagnetic events until a failure occurs (indicated by the LEDs). ESD: Electrostatic discharge (positive and negative) is applied on all pins of the device until a functional disturbance occurs. This test conforms with the IEC 61000-4-2 standard. FTB: A burst of fast transient voltage (positive and negative) is applied to VDD and VSS through a 100 pF capacitor, until a functional disturbance occurs. This test conforms with the IEC 61000-4-4 standard. A device reset allows normal operations to be resumed. The test results are given in the table below based on the EMS levels and classes defined in application note AN1709. Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular. Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application. Prequalification trials: Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015). Table 34. Symbol VFESD EMS data Parameter Conditions Level/ Class 3B 3B 4A Voltage limits to be applied on any I/O pin to LQFP32, VDD = 3.3 V induce a functional disturbance Fast transient voltage burst limits to be applied through 100 pF on VDD and VSS pins to induce a functional disturbance LQFP32, VDD = 3.3 V, fHSI LQFP32, VDD = 3.3 V, fHSI/2 VEFTB Doc ID 15275 Rev 7 61/77 Electrical parameters STM8L101xx Electromagnetic interference (EMI) Based on a simple application running on the product (toggling 2 LEDs through the I/O ports), the product is monitored in terms of emission. This emission test is in line with the norm SAE J 1752/3 which specifies the board and the loading of each pin. Table 35. Symbol EMI data (1) Parameter Conditions Monitored frequency band 0.1 MHz to 30 MHz 30 MHz to 130 MHz 130 MHz to 1 GHz SAE EMI Level Max vs. Unit 16 MHz -3 -6 -5 1 dBV SEMI Peak level VDD = 3.6 V, TA = +25 C, LQFP32 conforming to IEC61967-2 1. Not tested in production. Absolute maximum ratings (electrical sensitivity) Based on two different tests (ESD and LU) using specific measurement methods, the product is stressed in order to determine its performance in terms of electrical sensitivity. For more details, refer to the application note AN1181. Electrostatic discharge (ESD) Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts*(n+1) supply pin). One model can be simulated: Human Body Model. This test conforms to the JESD22-A114A/A115A standard. Table 36. Symbol VESD(HBM) VESD(CDM) ESD absolute maximum ratings Ratings Electrostatic discharge voltage (human body model) Electrostatic discharge voltage (charge device model) Conditions Maximum value (1) 2000 TA = +25 C 1000 V Unit 1. Data based on characterization results, not tested in production. 62/77 Doc ID 15275 Rev 7 STM8L101xx Electrical parameters Static latch-up LU: 2 complementary static tests are required on 10 parts to assess the latch-up performance. A supply overvoltage (applied to each power supply pin) and a current injection (applied to each input, output and configurable I/O pin) are performed on each sample. This test conforms to the EIA/JESD 78 IC latch-up standard. For more details, refer to the application note AN1181. Electrical sensitivities Parameter Static latch-up class Class II Table 37. Symbol LU 9.4 Thermal characteristics The maximum chip junction temperature (TJmax) must never exceed the values given in Table 16: General operating conditions on page 40. The maximum chip-junction temperature, TJmax, in degrees Celsius, may be calculated using the following equation: TJmax = TAmax + (PDmax x JA) Where: TAmax is the maximum ambient temperature in C JA is the package junction-to-ambient thermal resistance in C/W PDmax is the sum of PINTmax and PI/Omax (PDmax = PINTmax + PI/Omax) PINTmax is the product of IDD and VDD, expressed in Watts. This is the maximum chip internal power. PI/Omax represents the maximum power dissipation on output pins Where: PI/Omax = (VOL*IOL) + ((VDD-VOH)*IOH), taking into account the actual VOL/IOL and VOH/IOH of the I/Os at low and high level in the application. Doc ID 15275 Rev 7 63/77 Electrical parameters Table 38. Symbol STM8L101xx Thermal characteristics(1) Parameter Thermal resistance junction-ambient UFQFPN 20 - 3 x 3 mm - 0.6 mm Thermal resistance junction-ambient LQFP 32 - 7 x 7 mm Value 102 60 22 70 110 Unit C/W C/W C/W C/W C/W JA Thermal resistance junction-ambient WFQFPN 32 - 5 x 5 mm Thermal resistance junction-ambient WFQFPN 28 - 4 x 4 mm Thermal resistance junction-ambient TSSOP 20 1. Thermal resistances are based on JEDEC JESD51-2 with 4-layer PCB in a natural convection environment. 64/77 Doc ID 15275 Rev 7 STM8L101xx Package characteristics 10 10.1 Package characteristics ECOPACK In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK(R) packages, depending on their level of environmental compliance. ECOPACK(R) specifications, grade definitions and product status are available at: www.st.com. ECOPACK(R) is an ST trademark. 10.2 Package mechanical data Figure 38. WFQFPN32 recommended footprint(1)(3) Figure 37. WFQFPN32 - 32-lead very very thin fine pitch quad flat no-lead package outline (5 x 5)(1)(2) Seating plane C A ddd C A3 A1 D e 9 8 16 17 E2 b E 1 32 24 L Pin # 1 ID R = 0.30 D2 Bottom view L A0A3_ME 1. Drawing is not to scale. 2. The exposed pad must be soldered to the PCB. It is recommended to connect it to VSS. 3. Dimensions are in millimeters. Table 39. WFQFPN32 - 32-lead very very thin fine pitch quad flat no-lead package (5 x 5), package mechanical data(1) mm inches(2) Max 0.80 0.05 0.28 5.10 Min 0.0276 0 0.0071 0.1929 Typ 0.0295 0.0008 0.0091 0.1969 0.1378 Max 0.0315 0.0020 0.0110 0.2008 Dim. Min A(1) A1 b D D2 0.70 0.00 0.18 4.90 Typ 0.75 0.02 0.23 5.00 3.50 Doc ID 15275 Rev 7 65/77 Package characteristics Table 39. STM8L101xx WFQFPN32 - 32-lead very very thin fine pitch quad flat no-lead package (5 x 5), package mechanical data(1) (continued) mm inches(2) Max 5.10 3.70 Min 0.1929 0.1260 Typ 0.1969 0.1358 0.0197 0.50 0.0118 0.0157 0.0031 Number of pins 0.0197 Max 0.2008 0.1457 Dim. Min E E2 e L ddd 0.30 4.90 3.20 Typ 5.00 3.45 0.500 0.40 0.08 N 32 1. Thickness valid for the WFQFPN32 package in the sampling phase. In the production phase, the UFQFPN32 package will be used with a thickness equal to 0.6 mm. 2. Values in inches are converted from mm and rounded to 4 decimal digits. 66/77 Doc ID 15275 Rev 7 STM8L101xx Package characteristics Figure 39. LQFP32 - 32-pin low profile quad flat package outline (7 x 7)(1) Seating plane C A A2 Figure 40. LQFP32 recommended footprint(1)(2) 24 A1 ccc C D D1 D3 24 17 16 A1 L L1 K b c 0.25 mm Gage plane 17 16 25 25 32 1 E3 E1 E 9 8 32 Pin 1 identification 9 1 8 e 5V_ME 5V_FT 1. Drawing is not to scale. 2. Dimensions are in millimeters. Table 40. Dim. LQFP32- 32-pin low profile quad flat package (7x7), package mechanical data mm Min Typ Max 1.6 0.05 1.35 0.3 0.09 8.8 6.8 9 7 5.6 8.8 6.8 9 7 5.6 0.8 0.45 0.6 1 0.0 3.5 0.1 Number of pins 7.0 0.0 0.75 0.0177 9.2 7.2 0.3465 0.2677 1.4 0.37 0.15 1.45 0.45 0.2 9.2 7.2 0.002 0.0531 0.0118 0.0035 0.3465 0.2677 0.3543 0.2756 0.2205 0.3543 0.2756 0.2205 0.0315 0.0236 0.0394 3.5 0.0039 7.0 0.0295 0.3622 0.2835 0.0551 0.0146 Min inches(1) Typ Max 0.063 0.0059 0.0571 0.0177 0.0079 0.3622 0.2835 A A1 A2 b c D D1 D3 E E1 E3 e L L1 K ccc N 32 1. Values in inches are converted from mm and rounded to 4 decimal digits. Doc ID 15275 Rev 7 67/77 Package characteristics Figure 41. WFQFPN28 - 28-lead very very thin fine pitch quad flat no-lead package outline (4 x 4) STM8L101xx Figure 42. WFQFPN28 recommended footprint(1)(2) A ddd A3 A1 D e 7 14 15 b e E 1 L2 28 22 21 L1 DG_ME b 1. Drawing is not to scale 2. Dimensions are in millimeters Table 41. WFQFPN28 - 28-lead very very thin fine pitch quad flat no-lead package (4 x 4), package mechanical data(1) mm inches(2) Max 0.8 0.05 Min 0.0276 0 Typ 0.0295 0.0008 0.0079 0.3 0.0071 0.0098 0.1575 0.1575 0.0197 0.45 0.5 0.0098 0.0118 0.0138 0.0157 0.0031 Number of pins 0.0177 0.0197 0.0118 Max 0.0315 0.002 Dim. Min A(1) A1 A3 b D E e L1 L2 ddd 0.25 0.3 0.18 0.7 0 Typ 0.75 0.02 0.2 0.25 4 4 0.5 0.35 0.4 0.08 N 28 1. Thickness valid for the WFQFPN28 package in the sampling phase. In the production phase, the UFQFPN28 package will be used with a thickness equal to 0.6 mm. 2. Values in inches are converted from mm and rounded to 4 decimal digits. 68/77 Doc ID 15275 Rev 7 STM8L101xx Package characteristics Figure 43. UFQFPN20 3 x 3 mm 0.6 mm package outline (1) Figure 44. UFQFPN20 recommended footprint (1)(2) L1 D L4 e 5 b E 1 20 15 16 10 L2 11 e A3 ddd L3 A1 A A0A5_ME 1. Drawing is not to scale 2. Dimensions are in millimeters Table 42. Symbol UFQFPN20 3 x 3 mm 0.6 mm mechanical data millimeters Min Typ 3.000 3.000 0.550 0.020 0.152 0.500 0.500 0.300 0.550 0.350 0.150 0.200 0.180 0.250 0.050 0.300 0.0071 0.600 0.400 0.0197 0.0118 Max 3.100 3.100 0.600 0.050 0.0197 0 Min inches(1) Typ 0.1181 0.1181 0.0217 0.0008 0.006 0.0197 0.0217 0.0138 0.0059 0.0079 0.0098 0.002 0.0118 0.0236 0.0157 0.0236 0.002 Max D E A A1 A3 e L1 L2 L3 L4 b ddd 2.900 2.900 0.500 0 1. Values in inches are rounded to 4 decimal digits Doc ID 15275 Rev 7 69/77 Package characteristics STM8L101xx Figure 45. TSSOP20 - 20-lead thin shrink small package outline (1) Figure 46. TSSOP20 recommended footprint (1)(2) D 20 11 c E1 E 1 10 A1 A CP b e A2 L L1 TSSOP20-M 1. Drawing is not to scale 2. Dimensions are in millimeters Table 43. Dim. 20-lead thin shrink small package, mechanical data mm Min Typ Max 1.2 0.05 0.8 0.19 1 0.15 1.05 0.3 0.1 0.09 6.4 6.2 4.3 0.45 6.5 6.4 4.4 0.65 0.6 1 0 8 0 0.2 6.6 6.6 4.5 0.75 0.0035 0.252 0.2441 0.1693 0.1693 0.1693 0.2559 0.252 0.1732 0.0256 0.0236 0.0394 8 0.002 0.0315 0.0075 0.0394 Min Typ inches(1) Max 0.0472 0.0059 0.0413 0.0118 0.0039 0.0079 0.2598 0.2598 0.1772 0.0295 A A1 A2 b CP c D E E1 e L L1 a Number of pins N 20 1. Values in inches are converted from mm and rounded to 4 decimal digits. 70/77 Doc ID 15275 Rev 7 STM8L101xx Device ordering information 11 Device ordering information Figure 47. STM8L101xx ordering information scheme Example: STM8 L 101 F 3 U 6 A TR Product class STM8 microcontroller Family type L = Low power Sub-family type 101 = sub-family Pin count K = 32 pins G = 28 pins F = 20 pins Program memory size 2 = 4 Kbytes 3 = 8 Kbytes Package U = VFQFPN, WFQFPN or UFQFPN T = LQFP P = TSSOP Temperature range 3 = -40 C to 125 C 6 = -40 C to 85 C COMP_REF availability on UFQFPN20 A = COMP_REF available Blank = COMP_REF not available Shipping TR = Tape and reel Blank = Tray 1. For a list of available options (e.g. memory size, package) and orderable part numbers or for further information on any aspect of this device, please go to www.st.com or contact the ST Sales Office nearest to you. Doc ID 15275 Rev 7 71/77 STM8 development tools STM8L101xx 12 STM8 development tools Development tools for the STM8 microcontrollers include the full-featured STice emulation system supported by a complete software tool package including C compiler, assembler and integrated development environment with high-level language debugger. In addition, the STM8 is to be supported by a complete range of tools including starter kits, evaluation boards and a low-cost in-circuit debugger/programmer. 12.1 Emulation and in-circuit debugging tools The STice emulation system offers a complete range of emulation and in-circuit debugging features on a platform that is designed for versatility and cost-effectiveness. In addition, STM8 application development is supported by a low-cost in-circuit debugger/programmer. The STice is the fourth generation of full featured emulators from STMicroelectronics. It offers new advanced debugging capabilities including profiling and coverage to help detect and eliminate bottlenecks in application execution and dead code when fine tuning an application. In addition, STice offers in-circuit debugging and programming of STM8 microcontrollers via the STM8 single wire interface module (SWIM), which allows non-intrusive debugging of an application while it runs on the target microcontroller. For improved cost effectiveness, STice is based on a modular design that allows you to order exactly what you need to meet your development requirements and to adapt your emulation system to support existing and future ST microcontrollers. STice key features Occurrence and time profiling and code coverage (new features) Program and data trace recording up to 128 KB records Read/write on the fly of memory during emulation In-circuit debugging/programming via SWIM protocol 8-bit probe analyzer Power supply follower managing application voltages between 1.62 to 5.5 V Modularity that allows you to specify the components you need to meet your development requirements and adapt to future requirements Supported by free software tools that include integrated development environment (IDE), programming software interface and assembler for STM8. 72/77 Doc ID 15275 Rev 7 STM8L101xx STM8 development tools 12.2 Software tools STM8 development tools are supported by a complete, free software package from STMicroelectronics that includes ST Visual Develop (STVD) IDE and the ST Visual Programmer (STVP) software interface. STVD provides seamless integration of the Cosmic and Raisonance C compilers for STM8, which are available in a free version that outputs up to 16 Kbytes of code. 12.2.1 STM8 toolset STM8 toolset with STVD integrated development environment and STVP programming software is available for free download at www.st.com/mcu. This package includes: ST Visual Develop - Full-featured integrated development environment from ST, featuring Seamless integration of C and ASM toolsets Full-featured debugger Project management Syntax highlighting editor Integrated programming interface Support of advanced emulation features for STice such as code profiling and coverage ST Visual Programmer (STVP) - Easy-to-use, unlimited graphical interface allowing read, write and verify of your STM8 microcontroller's Flash program memory, data EEPROM and option bytes. STVP also offers project mode for saving programming configurations and automating programming sequences. 12.2.2 C and assembly toolchains Control of C and assembly toolchains is seamlessly integrated into the STVD integrated development environment, making it possible to configure and control the building of your application directly from an easy-to-use graphical interface. Available toolchains include: Cosmic C compiler for STM8 - Available in a free version that outputs up to 16 Kbytes of code. For more information, see www.cosmic-software.com. Raisonance C compiler for STM8 - Available in a free version that outputs up to 16 Kbytes of code. For more information, see www.raisonance.com. STM8 assembler linker - Free assembly toolchain included in the STVD toolset, which allows you to assemble and link your application source code. 12.3 Programming tools During the development cycle, STice provides in-circuit programming of the STM8 Flash microcontroller on your application board via the SWIM protocol. Additional tools are to include a low-cost in-circuit programmer as well as ST socket boards, which provide dedicated programming platforms with sockets for programming your STM8. For production environments, programmers will include a complete range of gang and automated programming solutions from third-party tool developers already supplying programmers for the STM8 family. Doc ID 15275 Rev 7 73/77 Revision history STM8L101xx 13 Revision history Table 44. Date 19-Dec-2008 Document revision history Revision 1 Intitial release. Added TSSOP28 package Modified packages on first page COMPx_OUT pins removed Added Figure 6: 28-pin TSSOP package pinout on page 17 Modified Section 9: Electrical parameters on page 37. Updated UBC[7:0] description in Section 7: Option bytes. Updated low power current consumption on cover page. Updated Table 13: Voltage characteristics, Table 20: Total current consumption and timing in Halt and Active-halt mode at VDD = 1.65 V to 3.6 V, Table 26: I/O static characteristics, Table 30: NRST pin characteristics, and Section 9.3.9: EMC characteristics. Updated PA1/NRST, PC0 and PC1 in Table 4: STM8L101xx pin description. Added ECC feature. Changed internal RC frequency to 38 kHz. Updated electrical characteristics in Table 16, Table 18, Table 19, Table 20, Table 22, Table 23, and Table 26. Corrected title on cover page. Changed VFQFPN32 to WFQFPN32 and updated Table 39: WFQFPN32 - 32-lead very very thin fine pitch quad flat no-lead package (5 x 5), package mechanical data. Updated Table 13, Table 26, and Table 33. Replaced WFQFPN20 3 x 3 mm 0.8 mm package by UFQFPN20 3 x 3 mm 0.6 mm package (first page, Table 16: General operating conditions on page 40, Table 38: Thermal characteristics on page 64, Section 10.2: Package mechanical data on page 65) Added one UFQFPN20 version with COMP_REF Modified Figure 40: LQFP32 recommended footprint(1) on page 67 Added IPROG values in Table 25: Flash program memory on page 48 Updated Table 31: SPI characteristics on page 56 Added STM8L101F3U6ATR part number in Section 4: Pin description on page 14 and in Figure 47: STM8L101xx ordering information scheme on page 71 Changes 22-Apr-2009 2 24-Apr-2009 3 14-May-2009 4 15-May-2009 5 74/77 Doc ID 15275 Rev 7 STM8L101xx Table 44. Date Revision history Document revision history (continued) Revision Changes Removed TSSOP28 package Modified consumption value on first page Added BEEP_CSR (address 00 50F3h) in Table 7: General hardware register map on page 25 TIM2_PSCRL replaced with TIM2_PSCR and CLK_PCKEN replaced with CLK_PCKENR in Table 7: General hardware register map on page 25 Added graphs in Section 9: Electrical parameters on page 37 Added tWU(AH) and tWU(Halt) max values in Table 20: Total current consumption and timing in Halt and Active-halt mode at VDD = 1.65 V to 3.6 V on page 43 Modified Table 20: Total current consumption and timing in Halt and Active-halt mode at VDD = 1.65 V to 3.6 V on page 43 Updated Table 22: HSI oscillator characteristics on page 45, Table 23: LSI oscillator characteristics on page 46 and Table 24: RAM and hardware registers on page 48 Modified Table 27: Output driving current (standard ports) on page 52 Removed note 1 in Table 37: Electrical sensitivities on page 63 Added note to Table 39: WFQFPN32 - 32-lead very very thin fine pitch quad flat no-lead package (5 x 5), package mechanical data on page 65 and Table 41: WFQFPN28 - 28-lead very very thin fine pitch quad flat nolead package (4 x 4), package mechanical data on page 68 12-Jun-2009 6 Doc ID 15275 Rev 7 75/77 Revision history Table 44. Date STM8L101xx Document revision history (continued) Revision Changes Added STM8L101F2U6ATR, STM8L101G2U6ATR and STM8L101G3U6ATR part numbers Modified Section 2: Description on page 7. Modified Table 2: Device features on page 8 (Flash) Modifiied Figure 1: STM8L101 device block diagram on page 9 Modified Section 3.5: Memory on page 11 Added note below Figure 2: Standard 20-pin UFQFPN package pinout on page 14 and Figure 5: Standard 28-pin WFQFPN package pinout on page 17 Added Figure 6: 28-pin WFQFPN package pinout for STM8L101G3U6ATR and STM8L101G2U6ATR part numbers on page 18 Modified reset values for Px_IDR registers in Table 6: I/O Port hardware register map on page 24 Added Section 6: Interrupt vector mapping on page 32 Modified OPT numbers in Section 7: Option bytes on page 34 Modified OPT2 in Table 10: Option bytes on page 34 Added Section 8: Unique ID on page 36 TIM_IR pin replaced with IR_TIM pin Modified Table 20: Total current consumption and timing in Halt and Active-halt mode at VDD = 1.65 V to 3.6 V on page 43 Modified Figure 15: Typ. IDD(Halt) vs. VDD @ fCPU = 2 MHz and 16 MHz @4 temperatures on page 43 and Figure 19: Typical LSI RC frequency vs. VDD @ 4 temperatures on page 47 Modified Table 27: Output driving current (standard ports) on page 52 Updated Table 29: Output driving current (PA0 with high sink LED driver capability) on page 52 Modified : Functional EMS (electromagnetic susceptibility) on page 61 Modified conditions in Table 35: EMI data on page 62 Added note to Figure 37: WFQFPN32 - 32-lead very very thin fine pitch quad flat no-lead package outline (5 x 5) on page 65 Modified Figure 41: WFQFPN28 - 28-lead very very thin fine pitch quad flat no-lead package outline (4 x 4) on page 68 Added Figure 44: UFQFPN20 recommended footprint (1) on page 69 Added Figure 46: TSSOP20 recommended footprint (1) on page 70 CMP replaced with COMP 07-Sep-2009 7 76/77 Doc ID 15275 Rev 7 STM8L101xx Please Read Carefully: Information in this document is provided solely in connection with ST products. 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The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. (c) 2009 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com Doc ID 15275 Rev 7 77/77 |
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